A5020797317- Particle physics theoretical and experimental studies
- High-Energy Particle Collisions Research
- Particle Detector Development and Performance
- Quantum Chromodynamics and Particle Interactions
- Dark Matter and Cosmic Phenomena
- Radiation Detection and Scintillator Technologies
- Computational Physics and Python Applications
- Advanced Data Storage Technologies
- Cosmology and Gravitation Theories
- Network Packet Processing and Optimization
- Image Processing Techniques and Applications
- Algorithms and Data Compression
- Particle Accelerators and Free-Electron Lasers
- Microfluidic and Bio-sensing Technologies
- Astrophysics and Cosmic Phenomena
- Superconducting Materials and Applications
- Particle accelerators and beam dynamics
- CCD and CMOS Imaging Sensors
- Electrowetting and Microfluidic Technologies
- Distributed and Parallel Computing Systems
- Structural Analysis of Composite Materials
- Neutrino Physics Research
- Black Holes and Theoretical Physics
- Medical Image Segmentation Techniques
- Advanced Vision and Imaging
Aristotle University of Thessaloniki
2012-2023
European Organization for Nuclear Research
2021
Istituto Nazionale di Fisica Nucleare, Sezione di Perugia
2017-2018
Istituto Nazionale di Fisica Nucleare, Sezione di Pisa
2016-2018
FIZ Karlsruhe – Leibniz Institute for Information Infrastructure
2018
Institute of Nuclear Physics of Lyon
2018
Saha Institute of Nuclear Physics
2018
The University of Adelaide
2016-2018
University of Pisa
2016-2017
University of Perugia
2017
Edge detection is one of the most fundamental algorithms in digital image processing. The Canny edge detector implemented algorithm because its ability to detect edges even images that are intensely contaminated by noise. However, this a time consuming and therefore implementations difficult reach real response speeds. Especially nowadays where demand for high resolution processing constantly increasing, need fast efficient ever so present. A new parallel FPGA implementation proposed paper...
A machine vision implementation on a field-programmable gate array (FPGA) device for real-time microfluidic monitoring Lab-On-Chips is presented in this paper. The system designed to follow continuous or plug flows, which the menisci of fluids are always visible. discriminates between front "head" flow and back "tail" able flows with maximum speed 20 mm/sec circular channels diameter 200 μm (corresponding approx. 60 μl/sec). It be part complete Point-of-Care system, will portable operate...
The Fast TracKer (FTK) is an extremely powerful and very compact processing unit, essential for efficient Level 2 trigger selection in future high-energy physics experiments at the LHC. FTK employs Associative Memories (AM) to perform pattern recognition; input output data are transmitted over serial links Gbit/s reduce routing congestion board level. Prototypes of AM chip have been manufactured tested, preparation imminent design final version.
The associative memory (AM) system of fast tracker (FTK) processor has been designed for the tracking trigger upgrade to ATLAS detector at Conseil Europeen Pour La Recherche Nucleaire large hadron collider. performs pattern matching (PM) using hits particles in silicon tracker. AM is main processing element FTK and mainly based on use application-specified integrated circuits (ASICs) (AM chips) execute PM with a high degree parallelism. It finds track candidates low resolution which become...
This paper presents the characterization of new Associative Memory chip (version 7) designed and fabricated in 28 nm CMOS. The design aims at: enhancing links from/to FPGAs; increasing bandwidth thanks to full custom LVDS transceivers; reducing power consumption silicon area by means memory cells with full-custom approach. was submitted December 2016; prototypes were packaged a 17 × Ball Grid Array (BGA) standalone package. Prototype confirms functionality. final will be assembled System In...
The use of tracking information at the trigger level in LHC Run II period is crucial for and data acquisition system will be even more so as contemporary collisions that occur every bunch crossing increase III. Fast TracKer part ATLAS upgrade project; it a hardware processor provide Level-1 accepted event (100 kHz) within 100μs, full tracks with momentum low 1 GeV . Providing fast, extensive access to information, resolution comparable offline reconstruction, FTK help precise detection...
This paper presents an FPGA-based machine vision implementation for flow detection on Lab-on-Chip (LoC) experiments. The proposed system is designed to provide real-time information the LoC user about state of flows (flow coordinates and points interest) as well input controller. It uniquely compensate noise in video originating from non ideal lighting conditions or movement. achieves real time response videos 1Mpixel resolution frame-rates exceeding 60fps microfluidic with a maximum speed 20mm/sec.
A Real-Time demonstrator based on the ATCA Pulsar-IIB custom board and Pattern Recognition Mezzanine (PRM) has been developed as a flexible platform to test characterize low-latency algorithms for track reconstruction L1 Trigger generation in future High Energy Physics experiments. The extensively used Track-Trigger architecture use of Associative Memory ASICs PRM cards. flexibility makes it suitable explore other solutions fully high-performance FPGA device.
The extended use of tracking information at the trigger level in LHC is crucial for and data acquisition (TDAQ) system to fulfill its task.Precise fast important identify specific decay products Higgs boson or new phenomena, as well distinguish contributions coming from many collisions that occur every bunch crossing.However, track reconstruction among most demanding tasks performed by TDAQ computing farm; fact, complete full Level-1 accept rate (100 kHz) not possible.In order overcome this...
The Associative Memory (AM) system of the Fast TracKer (FTK) processor has been designed to perform pattern matching using as input data from silicon tracker in ATLAS experiment. AM is primary component FTK and ASIC technology (the chip) execute with a high degree parallelism. finds track candidates at low resolution that are seeds for full fitting. implementation named "Serial Link Processor" based on an extremely powerful network 2 Gb/s serial links sustain huge traffic data. This paper...
The increase of the luminosity in High Luminosity upgrade CERN Large Hadron Collider (HL-LHC) will require use Tracker information evaluation Level-1 trigger order to keep rate acceptable (i.e.: <; 1MHz). A custom real-time system be needed extract track within latency constraints (<;10usec). We developed prototype building block this system, Pattern Recognition Mezzanine (PRM) that combines power both Associative Memory ASICs and modern FPGA devices. architecture functionalities PRM are...
This paper presents a high performance median implementation targeting detection of microfluidic flows on Lab-on-Chips real-time machine vision implementation. We propose and implement novel architecture which calculates the 2D coordinates set "active pixels" in window generic size. The proposed takes full advantage FPGA's characteristics to achieve is part system achieves flow 1Mpixel input videos at 60fps. module itself flexible can be used for numerous applications achieving calculation...
The Fast Tracker (FTK) is an ATLAS trigger upgrade built for full event, low-latency, high-rate tracking. FTK core, made of 9U VME boards, performs the most demanding computational task. Associative Memory Board Serial Link Processor (AMB) and Auxiliary card (AUX), plugged on front back sides same slot, constitute Processing Unit (PU), which finds tracks using hits from 8 layers inner detector. PU works in pipeline with Second Stage (SSB), 12-layer by adding extra to identified tracks. In...
The increase of the luminosity in High Luminosity upgrade CERN Large Hadron Collider (HL-LHC) will require use Tracker information evaluation Level-1 trigger order to keep rate acceptable (i.e.: <;1MHz). In extract track within latency constraints (<;5μs), a custom real-time system is necessary. We developed prototype main building block this system, Pattern Recognition Mezzanine (PRM) that combines Associative Memory ASICs with modern FPGA devices. architecture, functionality and test...
Real time tracking is a key ingredient for online event selection at hadron colliders. The Silicon Vertex Tracker the CDF experiment and Fast ATLAS are two successful examples of importance dedicated hardware to reconstruct full events We present future evolution this technology, applications High Luminosity runs Large Hadron Collider where Data processing speed will be achieved with custom VLSI pattern recognition linearized track fitting executed inside modern FPGAs, exploiting deep...
The Fast Tracker (FTK) executes real-time tracking for online event selection in the ATLAS experiment. Data processing speed is achieved by exploiting pipelining and parallel processing. Track reconstruction executed two stages. first stage, implemented on custom application-specific integrated circuit (ASICs) called associative memory (AM) chips, performs pattern matching (PM) to identify track candidates low resolution. second field programmable gate arrays (FPGAs), builds PM results,...