A5067583318- Advanced Wireless Communication Techniques
- Error Correcting Code Techniques
- Cooperative Communication and Network Coding
- Algorithms and Data Compression
University of Electronic Science and Technology of China
2022-2023
The ultra-low hardware consumption feature of stochastic decoding has made it a potential candidate for the implementation low-density parity-check(LDPC) decoders. However, existing LDPC decoders still suffer from performance degradation and relatively high cycles caused by correlation among bit streams. In this paper, we propose Hybrid Stochastic(HS) decoding, which achieves performance, throughput, efficiency jointly using our proposed novel check node(CN) Two's Complement(TCS) variable...
Hybrid low-density parity-check (LDPC) decoding combines conventional Belief-Propagation (BP) algorithm with stochastic to achieve high performance and low complexity simultaneously. However, lossy inefficient stochastic-to-binary (S2B) conversion brings extra degradation latency. In this paper, a bit-serial updating based hybrid (BSSU-HD) is proposed, which employs fully correlated (FCS) check nodes (CNs) probability tracers assisted variable (VNs) accomplish accurate efficient S2B...
The size of the state metrics cache (SMC) has a predominant impact on overall hardware consumption Turbo decoder. This brief presents low complexity SMC reduction algorithm based proposed stochastic quantization (SQ) technique, which reduces by randomly quantizing to different small bit-width numbers. selection random source and updating method extrinsic information are further explored minimize performance loss caused reduction. simulation synthesis results show that can achieve best bit...