Deep Neural Networks (DNNs) are nowadays a common practice in most of the Artificial Intelligence (AI) applications. Their ability to go beyond human precision has made these networks milestone history AI. However, while on one hand they present cutting edge performance, other require enormous computing power. For this reason, numerous optimization techniques at hardware and software level, specialized architectures, have been developed process models with high performance power/energy...

Currently, Machine Learning (ML) is becoming ubiquitous in everyday life. Deep (DL) already present many applications ranging from computer vision for medicine to autonomous driving of modern cars as well other sectors security, healthcare, and finance. However, achieve impressive performance, these algorithms employ very deep networks, requiring a significant computational power, both during the training inference time. A single DL model may require billions multiply-and-accumulated...

In today’s world, ruled by a great amount of data and mobile devices, cloud-based systems are spreading all over. Such phenomenon increases the number connected broadcast bandwidth, information exchange. These fine-grained interconnected systems, which enable Internet connectivity for an extremely large facilities (far beyond current devices) go name Things (IoT). this scenario, devices have operating time is proportional to battery capacity, operations performed per cycle exchanged data....

A great interest has been gained in recent years by a new error-correcting code technique, known as "turbo coding", which proven to offer performance closer the Shannon's limit than traditional concatenated codes. In this paper, several very large scale integration (VLSI) architectures suitable for turbo decoder implementation are proposed and compared terms of complexity performance; impact on VLSI system parameters like state number, number iterations, rate evaluated different solutions....

Low-density parity-check codes (LDPC) are among the most powerful error correcting tools today available. For this reason they became very popular in several applications such as digital satellite broadcasting system (DVB-S2), wireless local area network (IEEE 802.11n) and metropolitan (802.16e). Whereas code-specific decoders have been proposed literature, implementation of a high performance yet flexible LDPC decoder still is challenging topic. This work presents novel formulation decoding...

Autonomous Driving (AD) related features provide new forms of mobility that are also beneficial for other kind intelligent and autonomous systems like robots, smart transportation, industries. For these applications, the decisions need to be made fast in real-time. Moreover, quest electric mobility, this task must follow low power policy, without affecting much autonomy mean transport or robot. These two challenges can tackled using emerging Spiking Neural Networks (SNNs). When deployed on a...

Flexible and reconfigurable architectures have gained wide popularity in the communications field. In particular, for physical layer are an attractive solution not only to switch among different coding modes but also achieve interoperability. This work concentrates on design of a architecture both turbo LDPC codes decoding. The novel contributions this paper are: i) tackling reconfiguration issue introducing formal systematic treatment that, best our knowledge, was previously addressed ii)...

This brief proposes a multiplierless VLSI architecture for the famous 9/7 wavelet filters. The novelty of this is possibility to compute 5/3 results into data path with reduced number adders compared other solutions. has been characterized in terms performance through simulations JPEG2000 environment and Implementation on 0.13-mum standard cell technology shows that proposed architectures requires amount logic excellent performance.

The quantum dot Cellular Automata (QCA) is an emerging nanotechnology that has gained significant research interest in recent years. Extremely small feature sizes, ultralow power consumption, and high clock frequency make QCA a potentially attractive solution for implementing computing architectures at the nanoscale. To be considered as suitable CMOS substitute, technology must able to implement complex real-time applications with affordable complexity. Low density parity check (LDPC)...

High speed architectures for finding the first two maximum/minimum values are of paramount importance in several applications, including iterative (e.g., turbo and low-density-parity-check) decoders. In this brief, stemming from a previous work, based on radix-2 solutions, we propose higher mixed radix implementations that improve architecture latency. Post place route results 180-nm CMOS standard cell technology show proposed achieve lower latency than solutions with moderate area increase.

This paper proposes a flexible and efficient implementation of the 2D N-point discrete cosine transform (DCT) for High Efficiency Video Coding (HEVC) standard. The DCT is implemented through Walsh-Hadamard (WHT) followed by Givens rotations. scheme exploited to derive an adaptive algorithm, which allows computing four different approximations ranging from complete WHT, selectively skipping some shows statistical analysis usage derives precomputation mechanism adaptively skip Each...

Motivated by a recently published robust geometric programming approximation, generalized approach for approximating efficiently the max* operator is presented. Using this approach, approximated means of generic and yet very simple max operator, instead using additional correction term as previous approximation methods require. Following that, several turbo decoding algorithms are obtained with optimal near-optimal bit error rate (BER) performance depending on single parameter, namely number...

Transformers' compute- intensive operations pose enormous challenges for their deployment in resource- constrained EdgeAI / tiny ML devices. As an established neural network compression technique, quantization reduces the hardware computational and memory resources. In particular, fixed-point is desirable to ease computations using lightweight blocks, like adders multipliers, of underlying hardware. However, deploying fully-quantized Transformers on existing general-purpose hardware, generic...

Wireless Sensor Networks are an emerging phenomenon in the research community. The design and development of network architectures nodes implementation fostering many activities. Due to their wide application fields pervasive employment possibilities, investigation novel classes wireless sensor is great concern. In this paper we presented a Power-Scalable Motion Estimation IP suitable for video-surveillance over Networks. proposed architecture can achieve low dynamic power, good video...

This brief proposes a novel low-complexity, efficient 9/7 wavelet filters VLSI architecture for image compression applications. The performance of hardware implementation the filter bank depends on accuracy coefficients representation. aim this work is to show that great complexity reduction with excellent can be achieved going through derivation taps values

Any cryptographic system strongly relies on randomness to ensure robust encryption and masking methods. True Random Number Generators play a fundamental role in this context. The National Institute of Standards Technology (NIST) the Bundesamt für Sicherheit der Informationstechnik (BSI) provide guidelines for designing reliable entropy sources fuel Bit Generators. This work presents highly parameterized, open-source implementation TRNG based ring oscillators, complemented by an optimized...

The use of "turbo codes" has been proposed for several applications, including the development wireless systems, where highly reliable transmission is required at very low signal-to-noise ratios (SNR). problem extracting best coding gains from these kind codes deeply investigated in last years. Also hardware implementation turbo a challenging topic, mainly due to iterative nature decoding process, which demands an operating frequency much higher than data rate; case design constraints became...

This paper proposes a general framework for the design and simulation of network-on-chip-based turbo decoder architectures. Several parameters in space are investigated, namely, network topology, parallelism degree, rate at which messages sent by processing nodes over network, routing strategy. The main results this analysis as follows: 1) most suited topologies to achieve high throughput with limited complexity overhead generalized de Bruijn Kautz 2) depending on requirements, different...

This paper conducts an extensive comparative study of state-of-the-art solutions for implementing the SHA-3 hash function. SHA-3, a pivotal component in modern cryptography, has spawned numerous implementations across diverse platforms and technologies. research aims to provide valuable insights into selecting optimizing Keccak implementations. Our encompasses in-depth analysis hardware, software, software–hardware (hybrid) solutions. We assess strengths, weaknesses, performance metrics each...