Binarized Neural Networks (BNNs) can significantly reduce the inference latency and energy consumption in resource-constrained devices due to their pure-logical computation fewer memory accesses. However, training BNNs is difficult since activation flow encounters degeneration, saturation, gradient mismatch problems. Prior work alleviates these issues by increasing bits adding floating-point scaling factors, thereby sacrificing BNN's efficiency. In this paper, we propose use distribution...

Deep Neural Networks (DNNs) have been adopted in many systems because of their higher classification accuracy, with custom hardware implementations great candidates for high-speed, accurate inference. While progress achieving large scale, highly DNNs has made, significant energy and area are required due to massive memory accesses computations. Such demands pose a challenge any DNN implementation, yet it is more natural handle platform. To alleviate the increased demand storage energy,...

Application-specific integrated circuit (ASIC) implementations for Deep Neural Networks (DNNs) have been adopted in many systems because of their higher classification speed. However, although they may be characterized by better accuracy, larger DNNs require significant energy and area, thereby limiting wide adoption. The consumption is driven both memory accesses computation. Binarized (BNNs), as a trade-off between accuracy consumption, can achieve great reduction, good large due to its...

Deep Neural Networks (DNNs) have been adopted in many systems because of their higher classification accuracy, with custom hardware implementations great candidates for high-speed, accurate inference. While progress achieving large scale, highly DNNs has made, significant energy and area are required due to massive memory accesses computations. Such demands pose a challenge any DNN implementation, yet it is more natural handle platform. To alleviate the increased demand storage energy,...

Hardware security-related threats such as the insertion of malicious circuits, overproduction, and reverse engineering are increasing concern in IC industry. To mitigate these threats, various design-for-trust techniques have been developed, including sequential logic locking. Sequential locking protects a non-scanned design by employing key-controlled entrance FSM, transitions, or combination both techniques. Current methods for characterizing (attacking) security sequentially locked...

To improve the throughput and energy efficiency of Deep Neural Networks (DNNs) on customized hardware, lightweight neural networks constrain weights DNNs to be a limited combination (denoted as k ϵ {1, 2}) powers 2. In such networks, multiply-accumulate operation can replaced with single shift operation, or two shifts an add operation. provide even more design flexibility, for each convolutional filter optimally chosen instead being fixed every filter. this paper, we formulate selection...

Hardware implementations of deep neural networks (DNNs) have been adopted in many systems because their higher classification speed. However, while they may be characterized by better accuracy, larger DNNs require significant energy and area, thereby limiting wide adoption. The consumption is driven both memory accesses computation. Binarized (BNNs), as a tradeoff between accuracy consumption, can achieve great reduction good for large due to regularization effect. BNNs show poor when...

A comprehensive investigation of new integrated circuit design and fabrication technologies is crucial for yielding reliable parts. Prior work proposed a novel logic characterization vehicle called the Carnegie Mellon Logic Characterization Vehicle (CM-LCV), an implementation flow that ensures test chip to be product-like with near optimal testability diagnosability. This describes enhanced methodology CM-LCV not only guarantees 100% intra-cell defect all standard cells but also reflects...

Rapid yield learning in a new manufacturing process via test chips is greatly enhanced with "Design for Diagnosis" methodology. Prior work on logic-based chip design demonstrated an implementation flow that ensures 100% intra-cell fault coverage using minimal set. However, testability alone does not guarantee good diagnosability. Since diagnosis inherently function of design, it crucial the defect-level resolution and accuracy. This describes methodology Carnegie-Mellon Logic...

Recent research has focused on Deep Neural Networks (DNNs) implemented directly in hardware. However, larger DNNs require significant energy and area, thereby limiting their wide adoption. We propose a novel DNN quantization technique corresponding hardware solution, CompactNet that optimizes the use of resources even further, through dynamic allocation memory for each parameter. Experimental results MNIST CIFAR-10 datasets, show reduces requirement by over 80%, 12-fold, area 7-fold, when...

Application-specific integrated circuit (ASIC) implementations for Deep Neural Networks (DNNs) have been adopted in many systems because of their higher classification speed. However, although they may be characterized by better accuracy, larger DNNs require significant energy and area, thereby limiting wide adoption. The consumption is driven both memory accesses computation. Binarized (BNNs), as a trade-off between accuracy consumption, can achieve great reduction, good large due to its...

Continued scaling of semiconductor fabrication processes has made achieving yield targets increasingly difficult. The design and various types test vehicles is one approach for enabling fast learning. Recent work introduced the Carnegie Mellon logic characterization vehicle (CM-LCV). CM-LCV methodology uses regularity existing testability theory to produce logic-based designs that are both highly testable diagnosable. For be effective learning, it must reflect characteristics actual product...

Fast yield ramping in a new technology to meet aggressive time-to-market deadlines requires comprehensive design and fabrication methodology for silicon test structures that systematically explores validates the technology. Prior work proposed novel logic characterization vehicle (LCV), along with an implementation flow produces chip ensures demographics resemble real products, near-optimal testability diagnosability. This describes efficiently incorporates FEOL layout properties into easily...

Competitive position in the semiconductor field depends on yield which is becoming more challenging to achieve high levels due increasing complexity associated with design and fabrication of leading-edge integrated circuits (ICs). Consequently, test chips, especially full-flow logic are increasingly employed investigate complex interaction between layout features process before during product ramp. However, designing a quality chip can be time-consuming huge space. This work describes...

At advanced technology nodes, complex interactions between layout features and the process can lead to manufacturability issues that reduce yield. Due huge number of geometries inherent random logic, logic-only test chips are increasingly employed during yield ramp. This work describes a design methodology incorporates into an optimally testable full-flow logic chip. Experiments comparing properties among test-chip, benchmark, actual product designs demonstrate efficacy methodology....

To improve the throughput and energy efficiency of Deep Neural Networks (DNNs) on customized hardware, lightweight neural networks constrain weights DNNs to be a limited combination (denoted as $k\in\{1,2\}$) powers 2. In such networks, multiply-accumulate operation can replaced with single shift operation, or two shifts an add operation. provide even more design flexibility, $k$ for each convolutional filter optimally chosen instead being fixed every filter. this paper, we formulate...

To tackle the increasing testing power during built-in self-test (BIST) operations, this paper proposes a new test pattern generator (TPG). With proposed reconfigurable LFSR, Johnson counter, decompressor and XOR gate network, introduced TPG can produce single input change (SIC) sequences with few repeated vectors. The SIC minimize switching activities of circuit under (CUT). Simulation results on ISCAS benchmarks demonstrate that method effectively save power, does not impose high impact...

This paper proposes a unified solution to reduce test power and volume for test-per-scan schemes. With the self-testing using MISR Parallel SRSG (STUMPS) architecture developed reconfigurable Johnson counter, proposed pattern generator (TPG) applies two transition sequences all scan chains, primary inputs of circuit under (CUT) keep unchanged at most times. Therefore, switching activities both in combinational block chains can be reduced simultaneously. If generated vectors that do not...

Previous work on the Carnegie Mellon Logic Characterization Vehicle (CM-LCV) has achieved optimal testability for static fault models. This explores enhancements to CM- LCV that make delay faults optimally testable, with specific focus path model. Results from a design experiment indicate modified CM-LCV can achieve up 100% robust coverage, significant improvement estimated 55.22% coverage reference benchmark design.

Test vehicles of various types that aim to identify yield detractors are essential for maturing a new semiconductor process before high volume production. Due large number unpredictable geometries created by place-and-route, test focus on random logic the utmost importance. Prior work utilizes two-dimensional regular array blocks has demonstrated significant superiority over conventional approaches. In this work, third dimension is added ensure efficient diagnosis multiple defects frequently...

Test power and test overhead are crucial to VLSI SOC testing. This paper proposes a low cost pattern generator (TPG) for test-per-clock built-in self-test (BIST) scheme. The proposed method utilizes two-dimensional TPG bit-XOR array reduce area overhead, generates single input change (SIC) sequences transitions of the circuit under (CUT). Simulation results on ISCAS benchmarks demonstrate that can achieve high fault coverage effectively power.

Logic test chips are a key component of the yield learning process, which aim to investigate characteristics actual products that will be fabricated at high volume. Mathematically, design logic chip with such an objective may involve solving constrained under-determined equation for integer vector solution, is unfortunately, NP-hard. Existing methods not applicable due lack accuracy or computational complexity. We propose method called IPSA (Integer Programming via Sparse Approximation)...