A5006159218- Ferroelectric and Negative Capacitance Devices
- Low-power high-performance VLSI design
- Advanced Memory and Neural Computing
- Advancements in Semiconductor Devices and Circuit Design
- Numerical Methods and Algorithms
- Advanced Neural Network Applications
Southern University of Science and Technology
2022-2024
Huawei Technologies (China)
2022
There is an emerging need to design multi-precision floating-point (FP) accelerators for high-performance-computing (HPC) applications. The commonly-used methods are based on high-precision-split (HPS) and low-precision-combination (LPC) structures, which suffer from low hardware utilization ratio various multiple clock-cycle processing periods. In this brief, a new FP element (PE) developed with proposed bit-partitioning method. Minimized redundant bits operands achieved. PE supports...
Optimized deep neural network (DNN) models and energy-efficient hardware designs are of great importance in edge-computing applications. The architecture search (NAS) methods employed for DNN model optimization with mixed-bitwidth networks. To satisfy the computation requirements, convolution accelerators highly desired low-power high-throughput performance. There exist several to support multiply-accumulate (MAC) operations accelerator designs. low-bitwidth-combination (LBC) method improves...
Approximate computing is an emerging and effective method for reducing energy consumption in digital circuits, which critical energy-efficient performance improvement of edge-computing devices. In this paper, we propose a low-power DNN accelerator with novel signed approximate multiplier based on probability-optimized compressor error compensation. The customized partial product matrix (PPM) operands, gets the optimal logic circuit after probabilistic analysis optimization. At same time,...
Approximate computing is an emerging and effective means of reducing energy consumption in digital circuits, which critical for improving the efficiency edge devices. In this paper, we propose a novel low power signed approximate multiplier based on sign-focus compressor error compensation. The customized partial product matrix operands. After probabilistic analysis, it reduced to simplest logic circuit. At same time, truncate N-I columns perform By synthesis evaluation, proposed saves...