A5007804454- Radio Frequency Integrated Circuit Design
- Analog and Mixed-Signal Circuit Design
- Advancements in PLL and VCO Technologies
- Semiconductor Lasers and Optical Devices
- Advanced Power Amplifier Design
- Ultra-Wideband Communications Technology
- Wireless Body Area Networks
- Acoustic Wave Resonator Technologies
Imec the Netherlands
2020-2022
University of Twente
2017-2020
High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very for Internet-of-Things (IoT) receivers. We propose a zero-intermediate frequency (IF) receiver front-end architecture reduces by 2 × compared state-of-the-art improves >20-dB without compromising on other metrics. To achieve this, entire receive chain optimized. The low-noise...
Analog finite-impulse-response (AFIR) filtering is proposed to realize low-power channel selection filters for the Internet-of-Things receivers. High selectivity achieved using an architecture based on only a single-time-varying- transconductance and integration capacitor. The implemented as digital-to-analog converter programmable by on-chip memory. AFIR operating principle shown step step, including its complete transfer function with aliasing. filter bandwidth are highly through...
Using IR-UWB for accurate battery-powered localization requires low energy consumption and high interference resilience. The presented 802.15.4z transceiver features power thanks to its inverter-based RX architecture polar TX. two-stage distributed PLL enables simultaneous multi-channel reception, reducing the measurement time of localization. It consumes 8.9mW in TX mode 21.5mW/ch. while achieving -33dBm OOB blocker tolerance.
Upcoming Internet-of-Things (IoT) applications require low-power multi-standard RF receiver (RX) front-ends. Interference rejection becomes increasingly important as ever more devices compete in the scarce 10w-GHz spectrum. Typically, RXs do not possess very steep filtering [1]-[6]. On other hand, selective - e.g. using analog FIR or Filtering-by-Aliasing [7] have high power consumption, suitable for IoT applications. A recent Analog Finite-Impulse-Response (AFIR) filter [8] shows promising...
This brief presents a feedforward phase noise cancellation technique to reduce of the output clock signal phase-locked loop (PLL). It uses sub-sampling detector measure and variable time delay for cancellation. Both spurs are reduced. Analytical expressions have been derived that characterize performance this show its fundamental limitations. A subsampling PLL with as built-in feature is described. The has no stability requirements in contrast conventional architectures. reduction bandwidth...
Analog FIR filtering is proposed to improve the performance of a single stage g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -C channel selection filter for ultra low power Internet-of-Things receivers. The transconductor implemented as digital-to-analog converter; allowing varying transconductance in time, which results very sharp filter. manufactured 22-nm FDSOI and has core area 0.09 mm <sup...
Analog FIR filtering is proposed to improve the performance of a single stage g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> -C channel selection filter for ultra low power Internet-of-Things receivers. The transconductor implemented as digital-to-analog converter; allowing varying transconductance in time, which results very sharp filter. manufactured 22-nm FDSOI and has core area 0.09 mm <sup...