Qiuping Wu

ORCID: 0000-0003-3252-8611
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About
Contact & Profiles
Research Areas
  • Advanced Memory and Neural Computing
  • Advanced Neural Network Applications
  • Ferroelectric and Negative Capacitance Devices
  • VLSI and Analog Circuit Testing
  • Low-power high-performance VLSI design
  • CCD and CMOS Imaging Sensors
  • Neural Networks and Applications

Southern University of Science and Technology
2022-2024

Computing-In-memory (CIM) accelerators have the characteristics of storage and computing integration, which has potential to break through limit Moore's law bottleneck Von-Neumann architecture for convolutional neural networks (CNN) implementation improvement. However, performance CIM is still limited by conventional CNN architectures inefficient readouts. To increase energy-efficient performance, an optimized model required a low-power column parallel readout necessary edge-computing...

10.1109/jetcas.2022.3212314 article EN IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2022-10-05

Multi-bit-width neural network enlightens a promising method for high performance yet energy efficient edge computing due to its balance between software algorithm accuracy and hardware efficiency. To date, FPGA has been one of the core platforms deploying various networks. However, it is still difficult fully make use dedicated digital signal processing (DSP) blocks in accelerating multi-bit-width network. In this work, we develop state-of-the-art convolutional accelerator with novel...

10.1145/3543622.3573209 article EN 2023-02-10

Computing-In-memory (CIM) accelerators have the characteristics of storage and computing integration, which has potential to break through limit Moore's law bottleneck Von-Neumann architecture. However, performance CIM is still limited by conventional CNN architectures inefficient readouts. To increase energy-efficient performance, optimized model required low-power fully parallel readout necessary for edge-computing hardware. In this work, an ReRAM-based accelerator designed. Mixed-bit...

10.1109/apccas55924.2022.10090365 article EN 2022-11-11
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