Quantum spin Hall (QSH) materials promise revolutionary device applications based on dissipationless propagation of currents. They are two-dimensional (2D) representatives the family topological insulators, which exhibit conduction channels at their edges inherently protected against scattering. Initially predicted for graphene, and eventually realized in HgTe quantum wells, QSH systems so far, decisive bottleneck preventing is small bulk energy gap less than 30 meV, requiring cryogenic...

This paper presents a novel SiGe/Si tunneling field-effect transistor (TFET) which exploits line parallel with the gate electric field. The device makes use of selective and self-adjusted silicidation counter doped pocket within SiGe layer at source tunnel junction, resulting in high on-current Ion = 6.7 μA/μm supply voltage VDD −0.5 V constant subthreshold swing (SS) about 80 mV/dec over four orders magnitude drain-current Id.

Two-dimensional (2D) atom lattices provide model setups with Coulomb correlations that induce competing ground states. Here, SiC emerges as a wide-gap substrate reduced screening. We report the first artificial high-Z lattice on SiC(0001) by Sn adatoms, based experimental realization and theoretical modeling. Density-functional theory of our triangular structure closely reproduces scanning tunneling microscopy. Photoemission data show deeply gapped state (∼2 eV gap), and, calculations...

Doped HfO2 has become a promising candidate for non-volatile memory devices since it can be easily integrated into existing CMOS technology. Many dopants like Y, Gd, and Sr have been investigated the stabilization of ferroelectric HfO2. Here, we report fabrication capacitors comprising metal-insulator-metal structures with TiN bottom top electrodes using dopant Lu. Amorphous 5% Lu doped was deposited by pulsed laser deposition afterwards annealed to achieve ferroelectric, orthorhombic phase...

In this paper, we propose a recessed-gate tunneling field-effect transistor (TFET) to improve the on current of TFETs by increasing tunnel area with line tunneling. We investigate effects recessed-body thickness and doping level device performance. For optimal structures, our proposed n-TFET reaches 1.44 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> A/μm 3.22 xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> ON/OFF ratio. A...

The gate–source overlap length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{{\text {OV}}}$ </tex-math></inline-formula> ) in the line tunneling FET (L-TFET) can be used as a design parameter to improve analog circuit performance. In this paper, we investigate drain current notation="LaTeX">${I}_{D}$ dependence on , considering electrostatics of region. It is observed that increases with...

We present a comprehensive study on the formation and tuning of Schottky barrier NiGeSn metallic alloys Ge1-xSnx semiconductors. First, Ni metallization GeSn is investigated for wide range Sn contents (x = 0–0.125). Structural analysis reveals existence different poly-crystalline Ni3(GeSn)5 phases depending content. Electrical measurements confirm low sheet resistance 12 Ω/□ almost independent extracted from height in NiGeSn/GeSn/NiGeSn metal-semiconductor-metal diodes barriers holes below...

Preparation of SiC(0001) substrates is high relevance to graphene growth. Yet, if only a smooth surface could be achieved, heteroepitaxy many other two-dimensional materials comes into reach. Here we report novel approach hydrogen etching SiC, based on stepwise ultrapure H exposure with slow substrate cooling rates. For the first time, atomic evolution structure witnessed by scanning tunneling microscopy. A detailed picture gas phase chemistry emerges, such as zipper-like material desorption...

(Si)GeSn is an emerging group IV alloy system offering new exciting properties, with great potential for low power electronics due to the fundamental direct band gap and prospects as high mobility material. In this Article, we present a systematic study of HfO2/TaN high-k/metal gate stacks on ternary alloys temperature processes large scale integration Sn based alloys. Our investigations indicate that SiGeSn ternaries show enhanced thermal stability compared GeSn binaries, allowing use...

Thin-film Mg/Si(111) Schottky diodes are exposed to oxygen detect chemicurrents in the devices. The detected charge is created by nonadiabatic energy dissipation and due either internal exoemission currents or surface chemiluminescence induced photocurrents. Both contributions can be distinguished changing metal film thickness of device. Auger electron spectroscopy study uptake demonstrates that chemicurrent transients represent truly time dependent reaction rate at surface. Model...

This paper provides an experimental proof that both the ON-current <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> and subthreshold swing SS of Si(Ge)-based tunneling FETs (TFETs) drastically benefit from device architectures promoting line aligned with gate electrical field. A novel SiGe/Si heterostructure TFET is fabricated, making use a...

In this combined experiment and simulation study we investigate a SiGe/Si based gate-normal tunneling field-effect transistor (TFET) with pillar shaped contact to the junction which brings forth two significant advantages. The first, is improved electrostatics at boundary of helps diminish influence adverse paths, thus, substantially sharpens device turn on. second, simplified fabrication dual-metal gate using self-aligned process. We demonstrate feasibility process show positive effect in...

Views Icon Article contents Figures & tables Video Audio Supplementary Data Peer Review Share Twitter Facebook Reddit LinkedIn Tools Reprints and Permissions Cite Search Site Citation H. Nienhaus, D. Krix, S. Glass; Varying the Schottky barrier of thin film Mg∕H:p-Si(111) contacts: Properties applications. Journal Vacuum Science Technology A 1 July 2007; 25 (4): 950–954. https://doi.org/10.1116/1.2484574 Download citation file: Ris (Zotero) Reference Manager EasyBib Bookends Mendeley Papers...

We present the experimental analysis of planar Si p-tunnel FETs (TFETs) fabricated on ultrathin body Silicon Insulator (SOI) substrates by an optimized dopant implantation into silicide process. The average subthreshold swing such TFETs reaches 75 mV/decade over four orders magnitude drain current. Emphasis is placed capacitance- voltage TFETs. In contrast to simulation predictions, we provide evidence that contribution Cgs total gate capacitance increases at on-state, which in turn results...

The bandgap tunability of (Si)GeSn group IV semiconductors opens a new era in Si-technology. Depending on the Si/Sn contents, direct and indirect bandgaps range 0.4–0.8 eV can be obtained, offering broad spectrum both photonic low power electronic applications. In this work, we systematically studied capacitance–voltage characteristics high-k/metal gate stacks formed GeSn SiGeSn alloys with Sn-contents ranging from 0 to 14 at. % Si-contents 10 particularly focusing minority carrier inversion...

This letter presents an experimental capacitance-voltage C-V analysis for Si p-tunnel FETs (TFETs) fabricated on ultrathin body at various frequencies and temperatures. The capacitance distribution in TFETs is quite different compared with MOSFETs, due to inversion charges partitioning between source drain. Contrary predictions from simulations, we provide evidence the first time that contribution of gate-to-source C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...

The benefits of a gate-normal tunneling architecture in enhancing the on-current and average subthreshold swing field-effect transistors were scrutinized experiment through careful physical analysis Si0.50Ge0.50/Si heterostructure. In accordance with theoretical predictions, it is confirmed that governed by line scaling source-gate overlap area our devices. Our identifies early onset parasitic diagonal paths as most detrimental for low swing. By counter doping channel, this can be shifted...

This paper presents a Tunneling Field Effect Transistor concept with vertical SiGe/Si hetero tunneling junction utilizing design which promotes line in source-gate overlap region. By contrast, the influence of parasitic point is marginal structure, resulting sharp turn-on. We show that growth suitable layer stack and manufacturing device perfectly feasible provide first electrical measurements serving as proof concept. The route to enhancing performance by scaling dimensions adjusting...

In this paper we analyze the capabilities in terms of average subthreshold swing and on-current Si0.50Ge0.50/Siheterostructure n-TFETs with vertical tunneling path, utilizing an air bridge design to minimize source-drain leakage.We show that is line dominated proportional source-gate overlap area.In order obtain a low onsets diagonal point have be merged closely, which best achieved moderate counter doping channel.As result slopes 87 mV/dec over 4 decades Id Ion/Ioff ratios larger than 10 6...

In this paper we present a systematic study of GeSn n-FETs. First, process modules such as high-k metal gate stacks and NiGeSn - metallic contacts for use source/drain are characterized discussed. alloys different Sn content allow the capacitance-voltage (CV) contact characteristics both direct indirect bandgap semiconductors. We then n-FET devices have fabricated. The device characterization includes temperature dependent IV characteristics. As important step towards tunnel-FET Ge0.87Sn0.13...

Towards gate-all-around (GAA) FETs, we present the top-down realization of vertical Ge nanowires (NWs) with defect-free sidewall and perfect anisotropy. The NW patterns are transferred by a novel inductively coupled plasma reactive ion etching (ICP-RIE) technique. With optimized conditions, sub-60 nm diameter guaranteed while mitigating micro-trenching under-cutting effects. To further shrink diameter, digital is followed including multiple cycles self-limited O2 oxidation diluted HF...

In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. It is shown that the device achieves I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio of 5×10 <sup xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> considering (V = V xmlns:xlink="http://www.w3.org/1999/xlink">Ioff</sub> -0.5V) 0.8×10...