A5074853634- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Interconnection Networks and Systems
- Low-power high-performance VLSI design
- Ferroelectric and Negative Capacitance Devices
- Advanced Memory and Neural Computing
- Algorithms and Data Compression
- Advanced Neural Network Applications
- Green IT and Sustainability
- Modular Robots and Swarm Intelligence
- Network Packet Processing and Optimization
- Real-Time Systems Scheduling
- Environmental Impact and Sustainability
- Advanced Materials and Mechanics
- Image Enhancement Techniques
- Real-time simulation and control systems
- CCD and CMOS Imaging Sensors
- Distributed and Parallel Computing Systems
- Advanced Image and Video Retrieval Techniques
Brown University
2024-2025
University of Pittsburgh
2023-2024
John Brown University
2024
University of Maryland, College Park
2023
University of Electronic Science and Technology of China
2021
Dense matrix multiply (MM) serves as one of the most heavily used kernels in deep learning applications. To cope with high computation demands these applications, heterogeneous architectures featuring both FPGA and dedicated ASIC accelerators have emerged promising platforms. For example, AMD/Xilinx Versal ACAP architecture combines general-purpose CPU cores programmable logic (PL) AI Engine processors (AIE) optimized for AI/ML. An array 400 executing at 1 GHz can theoretically provide up to...
With the increase in computation intensity of chip, mismatch between layer shapes and available resource significantly limits utilization chip. Driven by this observation, prior works discuss spatial accelerators or dataflow architecture to maximize throughput. However, using could potentially execution latency. In work, we first systematically investigate two models: (1) sequentially (temporally) launch one monolithic accelerator, (2) spatially multiple accelerators. From observations, find...
As the increasing complexity of Neural Network(NN) models leads to high demands for computation, AMD introduces a heterogeneous programmable system-on-chip (SoC), i.e., Versal ACAP architectures featured with logic(PL), CPUs, and dedicated AI engines (AIE) ASICs which has theoretical throughput up 6.4 TFLOPs FP32, 25.6 TOPs INT16 102.4 INT8. However, higher level makes it non-trivial achieve performance even well-studied applications like matrix-matrix multiply. In this paper, we provide...
While vision transformers (ViTs) have shown consistent progress in computer vision, deploying them for real-time decision-making scenarios (<1 ms) is challenging. Current computing platforms like CPUs, GPUs, or FPGA-based solutions struggle to meet this deterministic low-latency requirement, even with quantized ViT models. Some approaches use pruning sparsity reduce the model size and latency, but often results accuracy loss. To address aforementioned constraints, work, we propose EQ-ViT, an...
Low precision quantization in convolutional neural network (CNN) inference has been proved effective for reducing computation complexity and bandwidth requirement. Mixed CNNs manage to benefit from low while maintaining accuracy. In this paper, we propose a Precision FPGA-based Overlay Processor (MP-OPU) fully leverage the advantages of mixed both conventional lightweight CNNs. The micro-architecture MP-OPU considers sharing core with weights activations improve efficiency. addition,...
Fast-evolving artificial intelligence (AI) algorithms such as large language models have been driving the ever-increasing computing demands in today's data centers. Heterogeneous with domain-specific architectures (DSAs) brings many opportunities when scaling up and out system. In particular, heterogeneous chiplet architecture is favored to keep system well reduce design complexity cost stemming from traditional monolithic chip design. However, how interconnect resources orchestrate chiplets...
Dense matrix multiply (MM) serves as one of the most heavily used kernels in deep learning applications. To cope with high computation demands these applications, heterogeneous architectures featuring both FPGA and dedicated ASIC accelerators have emerged promising platforms. For example, AMD/Xilinx Versal ACAP architecture combines general-purpose CPU cores programmable logic AI Engine processors optimized for AI/ML. With 400 AIEs, it provides up to 6.4 TFLOPs performance 32-bit...
Arbitrary-precision integer multiplication is the core kernel of many applications including scientific computing, cryptographic algorithms, etc. Existing acceleration arbitrary-precision includes CPUs, GPUs, FPGAs, and ASICs. To leverage hardware intrinsics low-bit function units (32/64-bit), can be calculated using Karatsuba decomposition, Schoolbook decomposition by decomposing two large operands into several small operands, generating a set multiplications that processed either in...
Fast-evolving artificial intelligence (AI) algorithms such as large language models have been driving the ever-increasing computing demands in today's data centers. Heterogeneous with domain-specific architectures (DSAs) brings many opportunities when scaling up and out system. In particular, heterogeneous chiplet architecture is favored to keep system well reduce design complexity cost stemming from traditional monolithic chip design. However, how interconnect resources orchestrate chiplets...
There is a growing call for greater amounts of increasingly agile computational power edge and cloud infrastructure to serve the computationally complex needs ubiquitous computing devices. Thus, an important challenge addressing holistic environmental impacts these next-generation systems. To accomplish this, life-cycle view sustainability advancements necessary reduce such as greenhouse warming gas emissions from choices. Unfortunately, decadal efforts address operational energy efficiency...
There is a growing call for greater amounts of increasingly agile computational power edge and cloud infrastructure to serve the computationally complex needs ubiquitous computing devices. Thus, an important challenge addressing holistic environmental impacts these next-generation systems. To accomplish this, life-cycle view sustainability advancements necessary reduce such as greenhouse warming gas emissions from choices. Unfortunately, decadal efforts address operational energy efficiency...
Dense matrix multiply (MM) serves as one of the most heavily used kernels in deep learning applications. To cope with high computation demands these applications, heterogeneous architectures featuring both FPGA and dedicated ASIC accelerators have emerged promising platforms. For example, AMD/Xilinx Versal ACAP architecture combines general-purpose CPU cores programmable logic AI Engine processors optimized for AI/ML. An array 400 executing at 1 GHz can provide up to 6.4 TFLOPS performance...
As the increasing complexity of Neural Network(NN) models leads to high demands for computation, AMD introduces a heterogeneous programmable system-on-chip (SoC), i.e., Versal ACAP architectures featured with logic (PL), CPUs, and dedicated AI engines (AIE) ASICs which has theoretical throughput up 6.4 TFLOPs FP32, 25.6 TOPs INT16 102.4 INT8. However, higher level makes it non-trivial achieve performance even well-studied applications like matrix-matrix multiply. In this paper, we provide...
Arbitrary-precision integer multiplication is the core kernel of many applications in simulation, cryptography, etc. Existing acceleration arbitrary-precision includes CPUs, GPUs, FPGAs, and ASICs. Among these accelerators, FPGAs are promised to provide both good energy efficiency flexibility. Surprisingly, our implementations, FPGA has lowest efficiency, i.e., 0.29x CPU 0.17x GPU with same generation fabrication. Therefore, key questions arise: Where do gains CPUs GPUs come from? Can...