A5015936744- Embedded Systems Design Techniques
- Interconnection Networks and Systems
- Parallel Computing and Optimization Techniques
- VLSI and Analog Circuit Testing
- Advanced Optical Sensing Technologies
- Formal Methods in Verification
- Optical Coherence Tomography Applications
- VLSI and FPGA Design Techniques
- Surface and Thin Film Phenomena
- Radiation Effects in Electronics
- Photonic and Optical Devices
- Analog and Mixed-Signal Circuit Design
- Quantum and electron transport phenomena
- Advanced Fluorescence Microscopy Techniques
- Physics of Superconductivity and Magnetism
- Advancements in PLL and VCO Technologies
University of Konstanz
2017
Siemens (Switzerland)
2002-2003
Low-temperature electronic transport measurements with high energy resolution require both effective low-pass filtering of high-frequency input noise and an optimized thermalization the system experiment. In recent years, elaborate filter designs have been developed for cryogenic low-level measurements, driven by growing interest in fundamental quantum-physical phenomena at scales corresponding to temperatures few millikelvin regime. However, a single concept is often insufficient thermalize...
A digital clock synthesizer consisting of standard cells with 0.5ppm frequency resolution for multimedia applications is implemented in a 0.6/spl mu/m CMOS process. The produces an output ranging from 11.1MHz to 12.5MHz 100MHz input clock. DLL-based calibration mechanism tracks PTV variations during operation.
Scalability and customization properties of IP modules demand for new approaches in functional verification. We present a novel simulation-based solution an Application-specific Instruction-set Processor (ASIP). Existing assembler code preselected by IP-configurable constraints forms the verification data base (reference stimuli). A behavioral "golden model" is used to derive expected responses suitable any possible configuration final ASIP (RTL) implementation. Cycle-based performed...
We present for the first time a fully integrated system-on-chip (SoC) pixel-based 3D range detection suited commercial applications. It is based on time-of-flight (ToF) principle, i.e. measuring phase difference of reflected pulse train. The product epc600 fabricated using dedicated process flow, called Espros Photonic CMOS. This integration makes it possible to achieve Quantum Efficiency (QE) >80% in full wavelength band from 520nm up 900nm as well very high timing precision sub-ns which...
During the development of a STM-1 add-drop multiplexer (ADM-1) we gained new experiences for efficient hardware/software co-design such complex telecommunication systems. The chosen partitioning between hardware and software can be seen as typical broadband applications. payload is processed in while management overhead treated software. To obtain an interface to get optimal real-time task scheduling all processes are interrupt driven. We developed processor core with stack architecture,...
In this paper we present an application-specific microprocessor core with a stack architecture optimized for use in broadband telecommunication ASICs. The was integrated application on the same die as complete data path of SDH add-drop multiplexer (ADM). It handles over 1 million interrupts per second from 29 asynchronous sources. Due to high interrupt rate extremely efficient context switching is required: only two extra cycles call. top four elements are directly accessable registers and...
Customizable microprocessors pose numerous design problems that arise from application-specific needs for data operations, word widths, storage capacities, and interfaces. We present a stack processor features customizable instruction set, extensive parametrization, synthesis model with separate core interface modules. Verification uses reference automatically derived generic the current parameter settings.
Hardware and software codesign flexibility requirements often necessitate embedded application-specific instruction-set processors in system-on-chip designs. Spaceman, a reusable stack-processor virtual component, offers customer-configurable instruction set; parameterizable bus widths, stack depths, access ranges; selectable interfaces.
We have implemented a SONET/SDH compatible 155 Mbit/s input block using new paradigm called programmable intellectual property. The module can be reconfigured by downloading software versions into the IP embedded processor. This concept offers maximum flexibility for both hard- and soft-IP modules.
A novel architecture for an ultra compact Add-Drop/Terminal-Multiplexer Synchronous Digital Hierarchy (SDH) telecommunication networks is reported. This new allows one to integrate all digital functions into ASIC (except the System Control Unit). The minimally configured complete system occupies only single card of size 235 mm/spl times/265 mm. If protection required two identical cards are used. key features obtain a chip solution scheme, data path which needs just buffer with integrated...
Two main aspects of multimedia SoC are addressed in this paper. First, a multiprocessor system employing reconfigurable hardware blocks with coarse and fine grain structures is introduced. It alleviates the tradeoff between computing performance circuit flexibility for wide range applications. Second, clock generator synchronous audio video interfaces presented. In order to provide high portability compatibility digital design flow it consists standard cells only. Integrated on 0.25 /spl...