A5101959755- VLSI and Analog Circuit Testing
- Analog and Mixed-Signal Circuit Design
- Advancements in PLL and VCO Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Building Energy and Comfort Optimization
- Iterative Learning Control Systems
- Low-power high-performance VLSI design
- Embedded Systems Design Techniques
- Environmental Impact and Sustainability
- Aeroelasticity and Vibration Control
- Advancements in Semiconductor Devices and Circuit Design
- Wind and Air Flow Studies
- Structural Analysis and Optimization
- Real-time simulation and control systems
- Manufacturing Process and Optimization
- VLSI and FPGA Design Techniques
National Research Council Canada
2020
Synchrotron soleil
2019
CEA LETI
2018
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
2018
Institut polytechnique de Grenoble
2018
CEA Grenoble
2018
Université Grenoble Alpes
2017
Centre National de la Recherche Scientifique
2016
Techniques of Informatics and Microelectronics for Integrated Systems Architecture
2016
La Rochelle Université
2007
This paper presents an on-chip stepwise ramp stimulus generator aimed at static linearity test applications for analog-to-digital converters (ADCs). The proposed is based on a simple switched-capacitor integrator with constant dc input. has been conveniently modified to produce very small integration gain proportional the capacitance difference of two capacitors, in such way that resulting signal output step size below least significant bit (LSB) target ADC under test. In order verify...
This paper presents the design of an efficient buffering solution for BIST applications static linearity test in high-speed high-performance ADCs. Relevant trade-offs buffer reusability are studied a nanometric CMOS technology. The circuit is devised to isolate on-chip generator output from high-frequency switching noise at sampling input ADC under test. stage, often overlooked literature, fact essential building block correct functionality applications. In order verify feasibility and...
This paper presents a self-testable BIST application for non-linearity test in high-speed high-performance ADCs nanometric CMOS technologies. The technique makes use of an on-chip low-frequency signal generator optimized toward high accuracy, followed by dedicated buffer based on resistive feedback amplifier. has two main features: it isolates the output from high-frequency switching noise at input sampling ADC under test, and allows robust injection controlled offset to apply...
This work presents an efficient modification of the classical servo-loop static test setup aimed at on-chip implementation reduced-code linearity techniques. The proposed modified provides a direct measurement width given ADC code without need integrated voltmeter. strategy is based on using controlled step-wise ramp stimulus generator for exciting under in such way that can be determined digital domain by simply counting number steps between two consecutive output transitions. Moreover,...
Morphing aircraft structures offer opportunities for the development of new aerospace technologies.A benchtopscale model a morphed leading edge composed carbon nanotube-polyurethane stretchable skin and 3D printed substructure was designed developed [1].To improve overall accuracy shape, design sub-structure is to be optimized.This paper describes material characterization sub-structure.The properties were determined through flexural testing coupons.The then calibrated finite element...