A5075512917- Advanced Memory and Neural Computing
- Advanced Neural Network Applications
- CCD and CMOS Imaging Sensors
- Innovative Human-Technology Interaction
- Parallel Computing and Optimization Techniques
- Interconnection Networks and Systems
- Radiation Effects in Electronics
Nanjing University
2022-2024
Pratt Institute
2024
This article addresses the challenges of excessive storage overhead and absence sparsity-aware design in Network-on-Chip (NoC)-based spatial deep neural network accelerators. The authors present a prototype chip that outperforms existing accelerators both energy area efficiency, demonstrated on TSMC 28-nm process technology. —Mahdi Nikdast, Colorado State University, USA —Miquel Moreto, Barcelona Supercomputing Center, Spain —Masoumeh (Azin) Ebrahimi, KTH Royal Institute Technology, Sweden...
Choices of dataflows, which are known as intra-core neural network (NN) computation loop nest scheduling and inter-core hardware mapping strategies, play a critical role in the performance energy efficiency NoC-based accelerators. Confronted with an enormous dataflow exploration space, this paper proposes automatic framework for generating optimizing full-layer-mappings based on two reinforcement learning algorithms including A2C PPO. Combining soft hard constraints, work transforms...
Hardware mapping plays a critical role in the performance of NoC-based accelerators running large-scale neural networks (NN). Confronted with enormous exploration space, traditional algorithms may find sub-optimal solutions. We conduct preliminary experiments to investigate impact different hardware mappings on communication latencies. Then, this paper proposes an Autonomous Optimal Mapping Exploration (AOME) architecture based two reinforcement learning algorithms. Combining soft and hard...
This study introduces an adaptive user interface generation technology, emphasizing the role of Human-Computer Interaction (HCI) in optimizing experience. By focusing on enhancing interaction between users and intelligent systems, this approach aims to automatically adjust layouts configurations based feedback, streamlining design process. Traditional involves significant manual effort struggles meet evolving personalized needs users. Our proposed system integrates with reinforcement...
Network-on-Chip (NoC) is a scalable on-chip communication architecture for the NN accelerator, but with increase in number of nodes, delay becomes higher. Applications such as machine learning have certain resilience to noisy/erroneous transmitted data. Therefore, approximate promising solution improving performance by reducing traffic loads under constraint acceptable maximum accuracy loss neural networks. It key issue balance result quality and NoC systems. The traditional only considers...
Data-intensive applications, such as machine learning and pattern recognition, result in heavy Network-on-Chip (NoC) communication loads a tremendous increase the latency. At same time, error-tolerant nature of these applications makes approximate an effective way to relieve sharp network This paper proposes adaptive congestion-aware mechanism (ACAC) that can alleviate congestion NoC systems loads. Our cycle-accurate simulations have shown proposed ACAC effectively reduces latency similar...