A5100708093- Integrated Circuits and Semiconductor Failure Analysis
- VLSI and Analog Circuit Testing
- Cloud Computing and Resource Management
- Engineering and Test Systems
- Software-Defined Networks and 5G
- IoT and Edge/Fog Computing
- Semiconductor Quantum Structures and Devices
- Advanced Computational Techniques and Applications
- Parallel Computing and Optimization Techniques
- Nanowire Synthesis and Applications
- Wireless Sensor Networks for Data Analysis
- Embedded Systems and FPGA Design
- Crystallization and Solubility Studies
- Caching and Content Delivery
- Real-Time Systems Scheduling
- Advanced Semiconductor Detectors and Materials
- Chemical and Physical Properties in Aqueous Solutions
- Low-power high-performance VLSI design
- Semiconductor Lasers and Optical Devices
- Vehicular Ad Hoc Networks (VANETs)
- Advanced Neural Network Applications
- Embedded Systems Design Techniques
- Real-time simulation and control systems
- Metal and Thin Film Mechanics
- Mobile Agent-Based Network Management
Alibaba Group (China)
2023-2024
Guizhou University
2008-2023
Peng Cheng Laboratory
2021
Guizhou Normal University
2008-2019
Sichuan Agricultural University
2019
Ningbo City College of Vocational Technology
2019
Hong Kong Polytechnic University
2010-2015
Beijing University of Technology
2013
Due to many attractive and unique properties, NAND flash memory has been widely adopted in mission-critical hard real-time systems some soft systems. However, the nondeterministic garbage collection operation makes it difficult predict system response time of each data request. This article presents Lazy-RTGC , a lazy mechanism for storage adopts two design optimization techniques: on-demand page-level address mappings, partial collection. On-demand mappings can achieve high performance...
In this paper, we propose to implement hybrid operating systems based on two-level hardware interrupts. We analyze and model the worst-case real-time interrupt latency for RTAI identify key component its optimization. Then, our methodology with interrupts by combining kernel time sharing OS (Operating System) kernel. Based methodology, discuss important issues implementation. Finally, a system called RTLinux-THIN (Real-Time LINUX Two-level Hardware INterrupts) ARM architecture Linux 2.6.9...
Background: Solasodine is a major bioactive ingredient in Solanum nigrum L. that has strong pharmacological characteristics. Therefore, the development of simple and effective extraction method for obtaining solasodine highly important. This study aims to provide rapid extracting from by microwave-assisted aqueous two-phase (MAATPE). Methods: First, high-performance liquid chromatography (HPLC) conditions were established detection solasodine. Then, system (ATPS) compositions examined. On...
In order to reduce the number of wires and cost automobile control system, Electronic controlling system power window is designed with PIC18F258, integrated CAN bus, as core, hardware structure flow chart software were presented. Compared point-to-point control, bus not only reduces wiring harness cost, but also makes more flexible fast. The experiment results show be reliable performance has advantages low-cost, low easy maintain.
This paper presents a low-power test scheme by using random single input change (RSIC) technique. By adding simple control logic on original linear feedback shift register (LFSR), the output of LFSR is modified, and RSIC sequence can be generated. The new optimizes switching activity circuit-under-test (CUT), then result in decrease power consumption. Initially, theoretical bases generation sequences are introduced. Then implementation for CC4028 integrated circuits analyzed. show that...
In order to effectively reduce the hidden trouble of electric window on automobile, many cars now use windows anti-pinch systems. It adds circuit based control module. PIC18F258 micro controller samples and process current motor. The method combining amplitude integral is used determine whether encounter obstacles, achieve function. Through several experiments, it shows that sensor-less system has good effects.
With CMOS device into the stage of very deep-submicron, testing power has been an important problem in VLSI design. In this paper, sources consumption for devices are analyzed and low test vector generator COMS is introduced. order to reduce switching activity rate internal nodes circuit-under-test (CUT), raise correlation between vector, approaches based on Random Single Input Change (RSIC) theory a configurable 2D-LFSR proposed, which can realize during testing, especially suitable BIST device.
In this paper, Sources of power consumption for CMOS logical circuits are analyzed and several BIST technologies low summarized. order to reduce the switching activity rate internal nodes in circuit-under-test raise correlation between testing vector, Random Single Input Change (RSIC)test theory is introduced. It can realize during without lossing fault coverage, especially suitable digital VLSI.
TranBichThuan Pham, Yi Wang, Renfa Li College of Information Science and Engineering, Hunan University, ChangSha, Hunan, China. estelle.ywang@gmail.com, lirenfa@vip.sina.com. Faculty Electronic Communication technology, Industrial University Hochiminh City, HoChiMinh, Vietnam. thuanphamtran@yahoo.com. Dept. Electrical Computer National Singapore, Singapore.
Rotation Region Proposal Networks (RRPN) are used to generate rotated proposals with the information of text angle for arbitrary oriented scene detection (STD). However, computational complexity RRPN inference is relatively high compared other methods, which makes it difficult massive deployment. In this paper, first full-stack FPGA-CPU heterogeneous system design RRPN-based STD algorithm proposed. A hardware/software partition method presented analyze and split tasks enhance computation...
The vSwitch, as a critical component for Virtual Machine (VM) network connectivity in cloud environments, has prompted increasing attention towards its forwarding performance. While software optimization schemes have limitations meeting the expanding capacity demands [11, 12, 15, 17, 18], hardware offloading architectures leveraging SoC, FPGA, and ASIC been proposed to transfer match-action workload [1, 3, 6, 7, 13, 16], addressing growing need capacity.
Abstract In view of the uncertainty data transmission due to irregular flow in network and limitation bandwidth resources, which makes control performance stability FlexRay decrease when is transmitted at high speed reliability safety system can not be guaranteed, this paper proposes a method based on Levenberg-Marquardt (LM) algorithm for neural predictive bus. The predict next moment operating state car according current working adaptively adjust task workload adapt changes vehicle load...
For matching lattice parameters, AlGaAs alloy is usually grown on a GaAs (001) substrate. The AlGaAs/GaAs multilayer structure has been widely used to manufacture various photoelectric and electronic devices. practical importance of atomic flat surfaces lies in improving the performances modern optoelectronic devices based structure. influence temperature flatness film not analyzed detail, so it very important prepare surface at an level by adjusting annealing temperature. In this paper, 15...
In this paper, a new BIST structure is presented, which generated by the LFSR modified. There no redundant single input jump test incentive, all possible vector combinations are covered, testing power reduced. Moreover, time do not increase and fault-coverage rate won't be affected. Experiment results on integrated circuit 74HC42 show that switching activity reduction can achieved up to 64% while achieving high fault coverage, especially suitable for of Integrated circuits.
The effect of different oxygen annealing treatments on the structural and electrical properties samples high temperature superconductor YBa 2 Cu 3 O 7δ (YBCO) synthesized by a biomimetic method has been studied. By annealing, deficiency resulting from synthesis in air can be adequately compensated. A two-stage process including step results sharper superconducting transition higher critical current density YBCO than only at low temperature, due to additional elimination carbon residues...
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This paper introduces a lower power built-in-self-test technology, which can effectively reduce the average consumption of under-test circuits during testing. Its basic theory is to improve structure test vector generator using ldquoAND/NOrdquo gate tree, therefore decreasing turn time ldquoimportant inputrdquo end among consumption. The result Benchmark experiment circuit emulation indicates this method may gain higher efficiency, and it's suitable for BIST digital integrated especially.