The cryptographic chip is widely used in government, military, finance, business and other fields, so the requirement of security very high. globalization integrated circuit supply chains has promoted rapid development industry, but also vulnerable to malicious modified by attacker, namely hardware Trojan implanted. paper proposed a efficient triggering method AES circuit. generated test vector set using optimal expand algorithm, which was for detecting judge whether exist Trojans....

Cryptographic chips usually act as a secure base for information security systems and provide corresponding cryptographic services. Trusted execution environment (TEE) techniques on-chip have been widely proposed effectively validated in academia industry. However, existing mainstream TEEs still certain risks, especially the face of emerging microarchitectural attacks. To address this issue, paper proposes strong isolation SoC architecture high-security application requirements based on...

The side-channel security of lattice-based post-quantum cryptography has gained extensive attention since the standardization cryptography. Based on leakage mechanism in decapsulation stage LWE/LWR-based cryptography, a message recovery method, with templates and cyclic rotation targeting decoding operation, was proposed. were constructed for intermediate state based Hamming weight model used to construct special ciphertexts. Using power during secret messages schemes recovered. proposed...

As an important implementation of Cryptographic algorithm, processor should be thought about the ability resistant power attack. In this paper we show a architecture, which automatically detects execution encryption algorithms, and interleaves cryptographic algorithm code with that dummy instructions to reduce correlations between leakage inside operations, thus make statistic analysis infeasible. Experiment verifies efficiency proposed method.

KASUMI is a block cipher with the Feistel network. This paper proposes small and efficiency hardware implementation for cipher, which core of 3GPP confidentiality algorithm f8, integrity f9. In designing hardware, we focused on optimizing FO/FI functions, are main components KASUMI. We propose three methods this optimization: using loop-structure in to reducing number function, implementing S7 S9-boxes combinational logic optimization extended key's generation.

Lightweight cryptographic algorithms play an important role in data security of applications Internet-Of-Things(IOT). To provide a cipher suitable for the IOT devices, we investigate performance QARMA block cipher. In this paper, proposed part-iterative architecture which integrates encryption and decryption operations. We implemented it on ASIC CMOS 55 nm technology, where max frequency 666.67MHz is obtained. The results show that our design has achieved 54% area reduced simultaneously 25...

Security problems of microsystem have gained widespread attention for its applications in many fields. However, current integration technologies cannot provide a security solution against physical invasive attack and side channel effectively. In this paper, novel silicon interposer structure with embedded trenches was proposed to achieve high integration. Chips were the metal shielding wires protected all directions, which formed Faraday cage. Experiment indicated that cage could shield...

Time randomization method is an effective way to counteract differential power analysis attack. By moving the cryptographic operations randomly in time domain, this could provide temporal shift curves. This paper proposed architecture for of AES. inserting registers among modules, change physical location through dynamical reconfiguration. The design realized using Altera's FPGA. Synthesis, placement and routing have been accomplished on 0.18 ¿m CMOS technology. result proves that...

Hardware security plays an important role in the information field and has gained significant interests from both industry academic communities. 3D integration technology, which enables ICs to be stacked vertical dimension provides smaller form factor higher performance, been extensively researched past. From reliability perspectives, technology also a unique perspective cope with threats occurred different phases of IC's life cycle. In this paper, advantages challenges have analyzed...

With the rapid development of integrated circuits and microsystems, security this IC industry is getting more attention [1]. Therefore, there may be malicious circuit insertion at various stages, resulting in functional failure, performance degradation. In order to prevent from being plugged into hardware Trojan, are now some Trojan protection technologies, including logic encryption, BISA technology so on. Among them, encryption makes it difficult for attackers insert Trojans rare nodes by...

Cache attacks exploit the hardware vulnerabilities inherent to modern processors and pose a new threat Internet of Things (IoT) devices. Intuitively, different cache parameter configurations directly impact attack effectiveness, but current research on this issue is not systematic or comprehensive enough. This paper’s primary focus evaluate how affect access-driven attacks. We build flexible configurable simulation verification environment based Chipyard framework. To reduce interference...

The test vector leakage assessment (TVLA) is a widely used side-channel power detection technology which requires evaluators to collect as many traces possible ensure accuracy. However, the total sample size of increases, amount redundant information will also increase, thus limiting efficiency. To address this issue, we propose principal component analysis (PCA)-TVLA-based framework realizes more advanced balance accuracy and Before implementing TVLA detect leakage, project original data...

With the significant attention to information security, mobile terminals such as smartphone always be demand for integrating cryptographic processor. In this paper, a high-efficiency reconfigurable processor is presented. Integrating small amounts of computing units designed by technology and developing instruction level parallelism different operations in block among multiple blocks, proposed architecture can improve performance algorithm under condition limited resources. The was simulated...

To realize the high-speed performance of processor, we need to research an efficient and flexible interconnection structure. In this paper, propose a multistage interconnect structure based on Crossbar in Coarse-Grained Reconfigurable Logic Array (CGRLA). Inner internet implements connection Functional operation unit flexibly outer data transmission different level function units. Through simulation verification, results show that put up is better than similar design there are some...

The security of cryptographic algorithms is great importance to information security. Power attack technology poses a serious threat the algorithm operations. In this paper composite field-based AES mask protection design proposed, realizing inversion operation in S-box through decomposition field. And random added each operations based on structure. Each intermediate value randomized, and cyclic shift used implement transformation round operation, thus improving ability resist power...

The paper described a novel improved version based on Integrated Operand Scanning (FIOS) algorithm, which would be beneficial to hardware implement in parallel. And new fault resistant scheme for our proposed algorithm was also shown this via comparing the intermediate variables with those recomputed during idle time. total cycle maybe reduce by about 40% of original one and capability checking errors proved most attractive.

Security of chips is the cornerstone hardware security and has drawn significant attention. With booming development advanced packaging, it provided a new approach to protect concept "security packaging ICs" been proposed recently. In this paper, was fully investigated. And, then, our attention paid on 3D which offers many opportunities chip mechanism. Additionally, reliability an important concern in inherent relationship with design. Therefore, were discussed together treated holistic...