A5004374867- Analog and Mixed-Signal Circuit Design
- Neuroscience and Neural Engineering
- Advanced Memory and Neural Computing
- CCD and CMOS Imaging Sensors
- Advancements in Semiconductor Devices and Circuit Design
- Radio Frequency Integrated Circuit Design
- Analytical Chemistry and Sensors
- Ferroelectric and Negative Capacitance Devices
- EEG and Brain-Computer Interfaces
- Neural Networks and Reservoir Computing
Eindhoven University of Technology
2021-2024
This paper presents a bio-inspired event-driven neuromorphic sensing system (NSS) capable of performing on-chip feature extraction and "send-on-delta" pulse-based transmission, targeting peripheral-nerve neural recording applications. The proposed NSS employs event-based sampling which, by leveraging the sparse nature electroneurogram (ENG) signals, achieves data compression ratio >125×, while maintaining low normalized RMS error 4% after reconstruction. consists three sub-circuits. A...
This work presents a power-efficient level crossing (LC) ADC designed to digitize sparse signals. It uses dynamically self-biased comparators, which require minimal current when the input voltage is far from decision threshold. also DAC architecture avoids signal attenuation commonly present in prior LC works, improving achievable SNDR. The prototype and implemented 65-nm CMOS technology, occupies an area of 0.0045 mm2. In 20 kHz bandwidth, LC-ADC achieves 64 dB Thanks proposed techniques...
This paper presents an event-driven neuromorphic sensing system capable of performing on-chip feature extraction and "send-on-delta" transmission for insertable cardiac monitoring. A background offset calibration improves the SNDR clockless level-crossing ADCs. fully synthesized spiking neural network extracts full ECG PQRST features with $\lt 1$ ms time precision. An body channel communication minimizes energy. The prototype is fabricated in 40nm CMOS consumes $28.2 \mu \mathrm{W}$ power.
This paper presents a level crossing ADC (LC-ADC) for biomedical applications. The uses dynamically biased comparators, which require minimal power when the input voltage is far away from decision threshold. results in >10x better efficiency compared to prior LC-ADCs converting sparse signals. In 16 kHz bandwidth, LC-ADC achieves 61.4 dB SNDR resulting an of 3 fJ/conv.step
Intracortical brain-computer interfaces offer superior spatial and temporal resolutions, but face challenges as the increasing number of recording channels introduces high amounts data to be transferred. This requires power-hungry serialization telemetry, leading potential tissue damage risks. To address this challenge, paper an event-based neural compressive telemetry (NCT) consisting 8 channel-rotating Δ-ADCs, event-driven serializer supporting a proposed ternary event representation...
In this work, we present a novel TIA with ultra-high transimpedance gain, achieved without the use of pseudo-resistors or off-chip resistors. The proposed approach overcomes conventional trade-offs between noise and gain in design resistive feedback. architecture makes transconductor negative feedback path to achieve impedance multiplication enable large amplification. Moreover, thanks dominant pole positioned at input TIA, circuit stability can be disentangled from when different capacitive...
This paper introduces a source degeneration technique using diode-connected transistor as device rather than conventional resistor improves the robustness against changes in biasing condition and temperature, removes need for calibration. The method is validated an analytical model, well with simulations, both at very low bias currents (where analytic exponential model matches behaviour of well) closer to threshold. shows improvement 6dB 20dB linearity when variation current temperature 20%...