The CEDAR real-time address block location system, which determines candidates for the of destination from a scanned mail piece image, is described. For each candidate (DAB), (ABL) system line segmentation, global orientation, skew, an indication whether appears to be handwritten or machine printed, and value indicating degree confidence that actually contains address. With 20-MHz Sparc processors, average time per combined hardware software components 0.210 seconds. located 89.0% addresses...

Wireless ad-hoc networks are vulnerable to various kinds of security threats and attacks due relative ease access wireless medium lack a centralized infrastructure. In this paper, we seek detect mitigate the denial service (DoS) that prevent authorized users from gaining networks. These affect availability connectivity hence reduce network performance. To end, propose novel cross-layer based intrusion detection system (CIDS) identify malicious node(s). Exploiting information available across...

Background Interest in integrating robotics within intensive care units (ICUs) has been propelled by technological advancements, workforce challenges, and heightened clinical demands, including during the COVID-19 pandemic. The integration of ICUs could potentially enhance patient operational efficiency amid existing challenges faced health professionals, high workload decision-making complexities. Objective This qualitative study aimed to explore ICU clinicians’ perceptions robotic...

In this paper, we study the following all-pair shortest path query problem: Given interval model of an unweighted graph n vertices, build a data structure such that each on (or its length) between any pair vertices can be processed efficiently (both sequentially and in parallel). We show that, after sorting input intervals by their endpoints, constructed O(n) time space; using structure, length two answered O(1) time, actual O(k) where k is number path. Furthermore, optimally parallel, O(log...

An application specific integrated circuit (ASIC) using a special-purpose content addressable memory that performs parallel search and multiple update (PSMU) operation is presented. This chip, referred to as (MUCAM), can 256, 8-b-wide locations in for target data all such with new within 50 ns. MUCAM has been developed image component labeling merging connected analyzer. It was fabricated 0.9- mu m CMOS technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML"...

The dense very deep submicron (VDSM) system on chips (SoC) face a serious limitation in performance due to reverse scaling of global interconnects. Interconnection techniques which decrease delay, delay variation and ensure signal integrity, play an important role the growth semiconductor industry into future generations. Current-mode low-swing interconnection provide attractive alternative conventional full-swing voltage mode signaling terms power noise immunity. In this paper, we present...

With technology scaling, combinational logic is becoming increasingly vulnerable to radiation strikes. Classical fault tolerant techniques mainly address single even upsets (SEUs). Robust designs capable of tolerating event transients (SETs) also are needed in lower nodes. In this paper, we present a novel SET mitigation scheme for flip-flops based on the time redundancy principle. The incurred area overhead due hardening minimized by reusing existing components (uses scan portion...

This paper describes the method for computer aided modelling of newly designed robot with aid 3D software. The static analysis also done by using conventional design procedures elements mechanical configurations base and arm explained in exhaustive manner. Nuclear waste storage steel canisters are often required regular maintenance surface inspection order to ensure goodness canisters. In this research work is doing same task help NDT system available at end arm. However, these types...

In this paper, we present a novel N-controlled SRAM (NC-SRAM) design for reducing the subthreshold leakage in cache and embedded memories using dual-V/sub t/ process. We combine use of high V/sub transistors path gating supply voltage to reduce unused cells. This circuit-level technique overcomes potential limitations existing techniques memory circuits. design, data stored cell is retained even when put stand-by mode, with no additional complexity or circuit overhead. Simulation results...

Designing a key management system is both important and challenging for wireless ad hoc networks. We have developed secure, scalable, decentralized robust solution using hybrid (symmetric/asymmetric) based methodology that well suited The nodes are grouped into clusters, keys distributed such intra-cluster communication secured symmetric cryptosystem inter-cluster an asymmetric cryptosystem. present detailed analysis of the simulation results. observe provides significant improvement in...

The design of fast, low power and robust sense amplifier circuits is a challenge for nanoscale SRAMs due to the increasing bit line capacitance process variations. Current sensing in promising achieve high-speed operation low-voltage application. In this paper, we propose variation tolerant, high performance scalable current that uses winner take all (WTA) approach SRAMs. Simulation worst-case threshold voltage mismatch on our WTA shows it could tolerate up 10% voltage, which expected within...

&lt;p&gt;&lt;em&gt;Abstract&lt;/em&gt; — The Segment Anything Model (SAM) is a state-of-the-art deep learning architecture for image seg- mentation that allows users to segment arbitrary objects in images using points, or bounding boxes. SAM uses novel two-stage approach first encodes the input into high-dimensional embedding, and then generates object masks embedding prompt. This ap- proach produce high-quality segmentation even were not seen during training, handle complex prompts with...

Chest radiography is a commonly utilized imaging technique for acquiring X-Ray (CXR) images due to its cost-effectiveness and role in diagnosing lung-related disorders. Nevertheless, interpreting CXR can be challenging, the process of separating lung field from valuable tool assessing diseases. While various segmentation methods exist, this study primarily focuses on META's latest Segment Anything Model (SAM). SAM an Artificial Intelligence (AI) model designed segment objects within image....

Accurate lung segmentation in chest x-ray images plays a pivotal role early disease detection and clinical decision-making. In this study, we introduce an innovative approach to enhance the precision of using Segment Anything Model (SAM). Despite its versatility, SAM faces challenge prompt decoupling, often resulting misclassifications, especially with intricate structures like clavicle. Our research focuses on integration spatial attention mechanisms within SAM. This enables model...

Wave pipelining is a digital design technique that can be applied to combinational logic circuits increase the throughput of system without increasing demand for storage space and power. The internal capacitances gates are used storage. gate library wave should have input independent, functionality independent load capacitance delays. Conventional static CMOS has dependent delay not suitable pipelining. requires path equalization along all paths from output. Delay balancing achieved in by...

A clock-biased local bit line (CB-LBL) scheme is presented to achieve high access speed and energy efficient operation for register files. Simulation results in 32nm high-k/metal gate CMOS predictive technology show 49.5% read latency reduction 39.4% power savings, with less than 5% impact on noise immunity within 1% increase area overhead. Additionally, CB-LBL can 99.8% parametric yield compared its original 47.6% (conventional LBL design), while being scalable.

A design method using CMOS Transmission-Gate Logic (TGL) is presented for wave-pipelined circuits implementation. The basic circuits, referred to as Wave-pipelined (WTGL), have complementary outputs driven by separate inverters. Timing analysis and simulation of the logic demonstrate that delay variations all input pattern combinations ace considerably reduced. Most importantly, can implement various functions with gate delays same magnitude. Practical are designed they verify advantages...

In this paper, we propose an application-driven ALU design methodology to achieve high level of power efficiency for modern microprocessors. We introduce a PN selection algorithm (PNSA) which enables designers select efficient dynamic modules different applications, based on the detailed analysis circuits. Experimental results ISCAS85 and 74X-Series benchmark circuits show that consumption 8-bit approach can be reduced by 54%-60% frequency levels as compared conventional design,...

Self-timed mesochronous interconnection scheme is presented for the interface between synchronous modules. It consists of a self-timed FIFO and local clock control circuit placed The receives data stream holds it until first synchronized at receiving module. After synchronization, input to module available through circuit. operates regardless amount skew An experimental design that demonstrates validity method.

As technology advances, keeping purely synchronous clocking scheme for a large, high-speed design becomes increasingly difficult, mainly due to the difficulties in controlling interconnection delays. This paper presents two-level synchronization scheme. A complex system is divided into several independently clocked modules. Communication between modules achieved by an called "self-timed mesochronous interconnection". The delay independence of eliminates need judicious control clock...

In this work, we present a security solution for wireless networks using novel low cost pseudo random number generator (PRNG). The PRNG is developed by superimposing certain or periodic waves such that the same generated at two different devices share secret key. numbers are used securing messages between devices. It shown capable of self synchronization, secure against most attacks and can be implemented both in hardware software. addition, lightweight ideal communication where may resource...

This paper addresses the problem of minimizing both leakage and glitch power by appropriately using dual-V/sub th/ buffer insertion (for path balancing) techniques, respectively. The is formulated as an integer linear program (ILP) with objective optimally assigning threshold voltage to gates minimize total then inserting delay buffers at appropriate positions glitches. ILP allows for tradeoff analysis including constraints where user specified thresholds well circuit performance can be...

ABSTRACT The objective of jamming attacks in a network is to deny service the communicating nodes, thus reducing throughput and availability. In this paper, we propose game theoretic framework for detecting wireless ad hoc networks. We formulate as two‐player, non‐cooperative analyze interaction between attacker monitoring nodes network. hybrid detection strategies at monitor node by using cross‐layer features attack detection. solve computing mixed‐strategy Nash equilibrium derive optimal...