Serkan Özdemir

ORCID: 0000-0001-5340-8534
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About
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Research Areas
  • Smart Grid Energy Management
  • Low-power high-performance VLSI design
  • Electric Power System Optimization
  • Auction Theory and Applications
  • Parallel Computing and Optimization Techniques
  • Auditing, Earnings Management, Governance
  • VLSI and FPGA Design Techniques
  • Semiconductor materials and devices
  • Manufacturing Process and Optimization
  • Transportation and Mobility Innovations
  • Electric Vehicles and Infrastructure
  • Education Practices and Challenges
  • Advancements in Semiconductor Devices and Circuit Design
  • Corporate Finance and Governance
  • Energy Load and Power Forecasting
  • IoT and GPS-based Vehicle Safety Systems
  • Infrastructure Resilience and Vulnerability Analysis
  • Quantum optics and atomic interactions
  • Educational Methods and Analysis
  • Global trade and economics
  • Public Administration and Governance
  • Turkish Literature and Culture
  • Problem Solving Skills Development
  • Working Capital and Financial Performance
  • Ottoman and Turkish Studies

Pennsylvania State University
2024

Cukurova University
2024

Leipzig University
2023

Erzincan University
2023

Pamukkale University
2015-2019

University of Duisburg-Essen
2015-2018

California Maritime Academy
2016

Dokuz Eylül University
2016

Usak University
2016

Yalova University
2015

One of the major issues faced by semiconductor industry today is that reducing chip yields. As process technologies have scaled to smaller feature sizes, yields dropped around 50% or less. This figure expected decrease even further in future technologies. To attack this growing problem, we develop four yield-aware micro architecture schemes for data caches. The first one called power-down (YAPD). YAPD turns off cache ways cause delay violation and/or excessive leakage. We also modify...

10.1109/micro.2006.52 article EN Proceedings of the ... annual International Symposium on Microarchitecture/Proceedings of the annual International Symposium on Microarchitecture 2006-12-01

Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. However, these mostly ignore effects of temperature on consumption. In this paper, first we show that can be suboptimal when thermal are considered. Particularly, propose a thermal-aware cache power-down technique minimizes density active parts by turning off alternating rows memory cells instead entire banks. The decrease lowers temperature, which return, reduces leakage parts....

10.1109/micro.2005.36 article EN 2006-10-11

Parameter variations are a major factor causing power-performance asymmetry in chip multiprocessors. In this paper, we analyze the effects of with-in-die (WID) process on multicore processors and then apply variable voltage island scheme to minimize power dissipation. Our idea is based observation that due variations, critical paths each core likely have different latencies resulting core-to-core (C2C) variations. As result, can operate correctly under supply levels, achieving an optimal...

10.1109/iccd.2007.4601891 article EN 2007-10-01

As transistor feature sizes continue to shrink intothe sub-90nm range and beyond, the effects of process variationson critical path delay chip yields have amplified. A commonconcept remedy variation is speed-binning, bywhich chips from a single batch are rated by discrete offrequencies sold at different prices. In this paper, we discussstrategies modify number in bins andhence enhance profits obtained them. Particularly, wepropose scheme that introduces small Substitute Cacheassociated with...

10.1109/l-ca.2008.3 article EN IEEE Computer Architecture Letters 2008-01-01

Previous works in computer architecture have mostly neglected revenue and/or profit, key factors driving any design decision. In this paper, we evaluate architectural techniques to optimize for revenue/profit. The continual trend of technology scaling and sub-wavelength lithography has caused transistor feature sizes shrink into the nanoscale range. As a result, effects process variations on critical path delay chip yields amplified. A common concept remedy is speed-binning, by which chips...

10.1109/micro.2008.4771807 article EN 2008-11-01

Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these can be suboptimal when thermal effects are considered. Then, propose a thermal-aware cache power-down technique minimizes density of active parts by turning off alternating rows memory cells instead entire banks. The decrease lowers temperature, which then exponentially reduces leakage. Thus, leakage is reduced addition to eliminated from turned...

10.1109/tvlsi.2007.896916 article EN IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2007-05-01

Local energy production and distributed storage facilities will take a leading position in the future smart grid along with challenge of sustainability. To cope this, simulation platforms are needed to analyze problems two-way data flow. The Power Trading Agent Competition (Power TAC) provides an open source, platform enable various studies from perspective Besides, annual competition is held which broker agents trade markets meet their supply demand. AgentUDE one competed TAC 2014 Final....

10.1109/wi-iat.2015.30 article EN 2015-12-01

As transistor feature sizes continue to shrink into the sub-90 nm range and beyond, effects of process variations on critical path delay chip yields have amplified. A common concept remedy variation is speed-binning, by which chips from a single batch are rated discrete frequencies sold at different prices. In this paper, we discuss strategies modify number in bins hence enhance profits obtained them. Particularly, propose scheme that introduces small Substitute Cache associated with each...

10.1109/l-ca.2007.8 article EN IEEE Computer Architecture Letters 2007-02-01

Local energy production and distributed storage facilities will take a prominent position in the future smart grid along with challenge of sustainability. To cope that, simulation platforms are needed order to analyze problems two-way data flow. The P ower Trading Agent Competition (Power TAC) provides an open source, platform enable various studies from perspective In this paper, we present AgentUDE, which competed Power TAC 2014 2015 Final games as broker agent. Here, create formalize...

10.3233/web-170358 article EN Web Intelligence 2017-05-08

Reduced tillage forms a subgroup of conservation tillage. In this system, chisel or disc tools are generally used for primary soil tillage, and milling machines, cultivators secondary seedbed preparation. The entire area is tillaged so that the plant residues on surface prone to surface. It provides significant fuel energy savings compared conventional due less machine traffic. order ensure sustainability, (using instead mouldboard plough works by turning soil) as an alternative development...

10.1051/bioconf/20248501007 article EN cc-by BIO Web of Conferences 2024-01-01

kontrol modellerinden COSO tüm boyutlarıyla açıklanmış, Sarbanes Oxley Kanunu (SOA) ile Amerikan Sermaye Piyasası'nın (SEC) şirketlerinden düzenli olarak istediği Finansal Raporlama Đlgili Đç Kontrol Raporu (Internal Control over Financial Reporting-ICFR) arasındaki ilişki üzerinde durulmuştur

10.17755/esosder.26059 article TR Elektronik Sosyal Bilimler Dergisi 2016-01-29

İşletmeler gelecek planları yapabilmek ve yönetim kararları alabilmek; şirket ortakları, yatırımcılar diğer üçüncü şahıslar ise işletme hakkında analizler için doğru detaylı finansal bilgiler içeren tablolara ihtiyaç duyarlar. Nakit akış tablosu BOBİ FRS tabi işletmelerin düzenlemek zorunda oldukları en önemli tablolardan biridir. akım “Doğrudan” “Dolaylı” yöntemlerden biri kullanılarak düzenlenebilmektedir. Literatürde nakit tablosunda doğrudan yöntemin kullanılmasının, ilişkili taraflar...

10.33206/mjss.527134 article TR MANAS Sosyal Araştırmalar Dergisi 2020-01-23

Dünya ticaret hacminin büyümesi ile beraber birden çok alanda faaliyet göstermeye başlayan şirketlerde, konsolide edilen finansal tablolardan elde bilgiler, kullanıcılara detayları gösterme konusunda yetersiz kalmaya başlamıştır. Bu sebeplerle son zamanlarda önemini arttıran bölümsel raporlama faaliyetleri Türkiye’de TFRS 8 Faaliyet Bölümleri Standardı şartları doğrultusunda uygulanmaktadır. raporlamada bir şablon önermemekte, şirketleri bölüm yapılarını oluşturmada ve bölümlendirilecek...

10.25095/mufad.396572 article TR Muhasebe ve Finansman Dergisi 2015-07-01

Entelektüel sermaye bir işletmenin hedeflerine ulaşmasında değer yaratan, rekabet üstünlüğü sağlayan maddi olmayan varlıkları, bilgileri ve becerileri ifade etmektedir. Bankalar ülkelerdeki ekonomik altyapıyı ayakta tutan tüm işletmeler gibi kâr temelli çalışan işletmelerdir. Günümüzde artan ortamında, bankaları pozitif ayrıştıracak kârlarını maksimize edecek en önemli faktörlerden biri entelektüel sermayeleridir. Bankalarda yönetiminin ilk aşaması doğru düzenli ölçümlemedir. İşletmelerde...

10.30794/pausbed.396896 article TR Pamukkale University Journal of Social Sciences Institute 2019-03-13

yüksekokulu öğrencilerinin zaman yönetimi becerilerinin belirlenmesi

10.17339/ejovoc.73399 article TR EJOVOC Electronic Journal of Vocational Colleges 2015-10-25
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