One of the major issues faced by semiconductor industry today is that reducing chip yields. As process technologies have scaled to smaller feature sizes, yields dropped around 50% or less. This figure expected decrease even further in future technologies. To attack this growing problem, we develop four yield-aware micro architecture schemes for data caches. The first one called power-down (YAPD). YAPD turns off cache ways cause delay violation and/or excessive leakage. We also modify...

Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance reliability. Various aging effects, such as negative bias temperature instability, cause continuous degradation during usage. In this work, we present a statistical analysis framework that characterizes the lifetime of nanometer-scale integrated circuits jointly considering fabrication-induced More specifically, our work focuses...

Thermal issues are a primary concern in the three-dimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized during 3D floorplanning, significantly increasing optimization complexity. Most existing floorplanners use combinatorial stochastic techniques, hampering performance scalability when used for floorplanning. In this work, we propose evaluate scalable, temperature-aware, force-directed fioorplanner called 3D-STAF. Force-directed...

Article Free Access Share on Simultaneous routing and buffer insertion with restrictions locations Authors: Hai Zhou Department of Computer Sciences, University Texas, Austin, TX TXView Profile , D. F. Wong I-Min Liu Electrical Engineering, Adnan Aziz Authors Info & Claims DAC '99: Proceedings the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 96–99https://doi.org/10.1145/309847.309885Published:01 June 1999Publication History 44citation315DownloadsMetricsTotal...

Routing is one of the most complex stages in back-end design process. Simple routing algorithms based on two global and detailed do not offer appropriate opportunities to address problems arising from signal delay, cross-talk process constraints. An intermediate stage track assignment between proves be an ideal place these problems. With this it possible use information efficiently aid router achieving wiring completions. In paper we formulate as a three process; routing, routing. We...

Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized during 3D floorplanning, significantly increasing optimization complexity. Most existing floorplanners use combinatorial stochastic techniques, hampering performance scalability when used for floorplanning. In this work, we propose evaluate scalable, temperature-aware, force-directed floorplanner called 3D-STAF. Force-directed...

While double patterning lithography (DPL) is still in active development, triple or even quadruple has recently been proposed for the next technology node. In this paper, we propose a pairwise coloring (PWC) method to tackle layout decomposition problem general multiple (MPL). The main idea reduce sets of concurrent bi-coloring problems. overall solution refined iteratively by applying pairs color per pass. One obvious advantage approach that existing DPL techniques can be reused seamlessly....

While double patterning lithography (DPL) is still in active development, triple or even quadruple has recently been proposed for the next technology node. In this paper, we propose a pairwise coloring (PWC) method to tackle layout decomposition problem general multiple (MPL). The main idea reduce sets of concurrent bi-coloring problems. overall solution refined iteratively by applying pairs color per pass. One obvious advantage approach that existing DPL techniques can be reused seamlessly....

The VLSI fabrication has entered the deep sub-micron era and communication between different components significantly increased. Interconnect delay become dominant factor in total circuit delay. As a result, it is necessary to start interconnect planning as early possible. In this paper, we propose method combine with floorplanning. Our approach based on Wong-Liu floorplanning algorithm. When positions, orientations, shapes of cells are decided, pin positions routing interconnects decided...

Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely over-constrains system and results solutions excessive penalties. Statistical timing have consequently emerged as a refinement of traditional static approach optimization. In this paper, we propose statistical gate sizing methodology yield improvement. We build models delays from library characterizations at multiple...

Due to the scaling down of device geometry and increasing frequency in deep submicron designs, crosstalk between interconnection wires has become an important issue very large scale integration (VLSI) layout design. In this paper, we consider avoidance during global routing. We present a routing algorithm based on new Steiner tree formulation Lagrangian relaxation technique. also give theoretical results complexity problem.

The Steiner Minimal Tree (SMT) problem is a very important in large scale integrated computer-aided design. Given n points on plane, an SMT connects these through some extra (called points) to achieve minimal total length. Even though there exist many heuristic algorithms for this problem, they have either poor performances or expensive running time. This paper records implementation of efficient algorithm that has worst case time O(nlogn) and performance close the Iterated 1-Steiner...

In this paper we address the problem of module selection during high-level synthesis. We present a heuristic algorithm for leakage power optimization based on maximum weight independent set problem. A dual threshold voltage (Vth) technique is used to reduce energy consumption in data flow graph. Experiments are performed data-path dominated test suite six benchmarks. Our approach achieves an average 70.9% reduction, which very close optimal results from Integer Linear Programming approach.

Obstacle-avoiding Steiner routing has arisen as a fundamental problem in the physical design of modern VLSI chips. In this paper, we present EBOARST, an efficient four-step algorithm to construct rectilinear obstacle-avoiding tree for given set pins and obstacles. Our contributions are fourfold. First, propose novel algorithm, which generates sparse spanning graphs efficiently. Second, fast minimum terminal construction step, dominates running time several existing approaches. Third,...

Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely over-constrains system and results solutions excessive penalties. Statistical timing have consequently emerged as a refinement of traditional static approach optimization. In this paper, we propose statistical gate sizing methodology yield improvement. We build models delays from library characterizations at multiple...

The modern era of embedded system design is geared toward the low-power systems. One way to reduce power in an application-specified integrated circuit (ASIC) implementation bit-width precision its computation units. This paper describes algorithms optimize bit widths fixed-point variables for low a SystemC-based ASIC environment. We propose optimal allocation algorithm two and greedy heuristic that works any number variables. are used automation converting floating-point SystemC programs...

In this paper, we formulate the generalized convex sizing (GCS) problem that unifies problems and applies to sequential circuits with clock-skew optimization. We revisit approach solve by Lagrangian relaxation, point out several misunderstandings in previous extend handle general delay functions GCS problems. identify a class of proper whose objective simplified dual are differentiable transform simultaneous optimization into problem. design an algorithm based on method feasible directions...

Approximate adder design has drawn wide attention as it can achieve good trade-offs between computation accuracy and cost. We observe that all existing approximate adders may produce completely incorrect result with up to 100% relative error. The big errors happen when higher bits have inconsistent views on certain lower carry-ins due long carry chain. In this paper, we build a theoretical model efficiently estimate the error characteristics of adders. Furthermore, present novel provable...

During the routing of global interconnects, macro blocks form useful regions which allow wires to go through but forbid buffers be inserted. They give restrictions on buffer locations. In this paper, we take these location into consideration and solve simultaneous maze insertion problem. Given a block placement defining pair pins (a source sink), polynomial time exact algorithm find buffered route from sink with minimum Elmore delay.

ACG (adjacent constraint graph) is invented as a general floorplan representation. It has advantages of both adjacency graph and floorplan: edges in an are between modules close to each other, thus the physical distance two can be measured directly graph; since graph, area module positions simply found by longest path computations. A natural combination horizontal vertical relations within one renders beautiful data structure with full symmetry. The direct correspondence geometrical...

Routing is one of the most complex stages in back-end design process. Simple routing algorithms based on two global and detailed do not offer appropriate opportunities to address problems arising from signal delay, cross-talk process constraints. An intermediate stage track assignment between proves be an ideal place these problems. With this it possible use information efficiently aid router achieving wiring completions. In paper we formulate as a three process; routing, routing. We...

Approximate adder design has drawn wide attention as it can achieve good trade-offs between computation accuracy and cost. We observe that all existing approximate adders may produce completely incorrect result with up to 100% relative error. The big errors happen when higher bits have inconsistent views on certain lower carry-ins due long carry chain. In this paper, we build a theoretical model efficiently estimate the error characteristics of adders. Furthermore, present novel provable...

Steiner Minimal Tree (SMT) problem is a very important in VLSI CAD. Given n points on plane, minimal tree connects these through some extra (called points) to achieve total length. Even though there exist many heuristic algorithms for this problem, they have either poor performances or expensive running times. This paper records an implementation of efficient algorithm that has worst case time O(n logn) and similar performance as the Iterated 1-Steiner algorithm. The efficiently combines...

Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem exacerbated by high-level automation tools that ignore increasingly important factors such as impact interconnect on area and power consumption integrated circuits. Bringing physical information up into logic level or even behavioral-level stages system essential to solve this problem. In paper, we present an incremental floorplanning synthesis system. integrates algorithms concurrently improve a...