We describe recent results obtained with AQUA, a mobile robot capable of swimming, walking and amphibious operation. Designed to rely primarily on visual sensors, the AQUA uses vision navigate underwater using servo-based guidance, also obtain high-resolution range scans its local environment. This paper describes some pragmatic logistic obstacles encountered, provides an overview basic capabilities vehicle associated sensors. Moreover, this presents first ever transition from swimming.

This paper describes an underwater walking robotic system being developed under the name AQUA, goals of AQUA project, overall hardware and software design, basic sensor packages that have been developed, some initial experiments. The robot is based on RHex hexapod uses a suite sensing technologies, primarily computer vision INS, to allow it navigate map clear shallow-water environments. sensor-based navigation mapping algorithms are use both artificial floating visual acoustic landmarks as...

Over the past few years, a new era of smart connected devices has emerged in market to enable future world Internet Things (IoT). A key requirement for IoT applications is power consumption allow very high autonomy case battery-powered systems. Depending on application, such will be most time low-power mode (sleep mode) and wake up only when there task accomplish (active mode). Emerging non-volatile memory technologies are seen as attractive solution design ultra-low-power Among these...

Spin transfer torque magnetic random access memory (STT-MRAM) possesses many desirable properties such as nonvolatility, fast speed, unlimited endurance, and good compatibility with CMOS fabrication process. ITRS has highlighted the potential of STT-MRAM one candidates for next-generation universal technology. However, both behaviors Magnetic Tunnel Junction (MTJ) transistor, which are two basic elements STT-MRAM, generally temperature dependent, threatening reliability, performance under...

Physically Unclonable Functions (PUFs) are emerging cryptographic primitives used to implement low-cost device authentication and secure secret key generation. Weak PUF s (i.e., devices able generate a single signature or deal with limited number of challenges) widely discussed in literature. One the most investigated solutions today is based on SRAMs. However, rapid development low-power, high-density, high-performance SoCs has pushed embedded memories their limits opened field memory...

Single-ISA heterogeneous multicore processors have gained increasing popularity with the introduction of recent technologies such as ARM big.LITTLE. These offer increased energy efficiency through combining low power in-order cores high performance out-of-order cores. Efficiently exploiting this attractive feature requires careful management so to meet demands targeted applications. In paper, we explore design those architectures based on big.LITTLE technology by modeling and in gem5 McPAT...

Lightweight cryptography has recently emerged as a strong requirement for any highly constrained connected device; encryption/decryption processes must strike the balance between speed, area, power efficiency, and security robustness. The aim of this paper is to study potential gains lightweight algorithms compared classic ones in hardware implementation. Advanced Encryption Standard (AES) standard, PRESENT very published GIFT are considered along with several optimized versions each one....

This paper describes a novel engine, called PE-ICE (parallelized encryption and integrity checking engine), enabling to guarantee confidentiality of data exchanged between SoC (system on chip) its external memory. The approach is based an existing block-encryption algorithm which the capability added. Simulation results show that performance overhead remains low (below 4%) compared block-encryption-only systems (which provide only).

Applications like 4G baseband modem require single-chip implementation to meet the integration and power consumption requirements. These applications demand a high computing performance with real-time constraints, low-power low cost. With rapid evolution of telecom standards increasing for multi-standard products, need flexible solutions is growing. The concept Multi-Processor System-on-Chip (MPSoC) well adapted enable hardware reuse between products multiple wireless in same device....

Owing to the flexibility they offer, soft-core processors are becoming an attractive alternative for embedded system designs. Through use of reconfigurable computing devices, such provides designers opportunity quickly uncover best design trade-offs and achieve specific application goals. The present work introduces Secret Blaze, a highly configurable open-source RISC processor. Details about its modular approach that aims strike balance between quality efficiency data path particularly...

Modern Field Programmable Gate Arrays (FPGAs) are built using the most advanced technology nodes to meet performance and power demands. This makes them susceptible various reliability challenges at nano-scale, in particular transistor aging. In this paper, an experimental analysis is made identify main parameters phenomena influencing degradation of FPGAs. For that purpose, a set controlled ring-oscillator-based sensors with different frequencies tunable activity control implemented on...

It has become increasingly challenging to respect Moore's well-known law in recent years. Energy efficiency and manufacturing constraints are among the main challenges current integrated circuits today. The energy issue is mainly due high leakage from CMOS transistors that used build almost all logic devices. As a result, performance limited few gigahertz power dissipation. A significant proportion of total spent on memory systems increasing trend embedding volatile into systems-on-chip New...

With forecasted hundreds of processing elements (PE), future embedded systems will be able to handle multiple applications with very diverse running constraints. In order avoid hot-spots and control the temperature tiles, dynamic voltage-frequency scaling (DVFS) can applied at PE level. At system level, it implies dynamically manage different couples each in obtain a global optimization. this article we present an approach based on game theory, which adjusts run-time frequency PE. It aims...

This paper describes the integration of a thermally assisted switching magnetic random access memory (TAS-MRAM) in FPGA design. The non-volatility latter is achieved through use tunneling junctions (MTJ) MRAM cell. A scheme used to write data MTJ device, which helps reduce power consumption during operation comparison writing classical device. Plus, such design should both and configuration time required at each up circuit SRAM based FPGAs. real reconfigurable (RTR) micro-FPGA using TAS-MRAM...

Multiprocessor Systems‐on‐Chips (MPSoCs) offer superior performance while maintaining flexibility and reusability thanks to software oriented personalization. While most MPSoCs are today heterogeneous for better meeting the targeted application requirements, homogeneous may become in a near future viable alternative bringing other benefits such as run‐time load balancing task migration. The work presented this paper relies on NoC‐based MPSoC framework we developed exploring scalable adaptive...

Applications like 4G baseband modem require single-chip implementation to meet the integration and power consumption requirements. These applications demand a high computing performance with real-time constraints, low-power low cost. With rapid evolution of telecom standards increasing for multi-standard products, need flexible solutions is growing. The concept Multi-Processor System-on-Chip (MPSoC) well adapted enable hardware reuse between products multiple wireless in same device....

The widening spectrum of applications and services provided by portable embedded devices brings a new dimension concerns in security. Most those systems (pay-TV, PDAs, mobile phones, etc.) make use external memory. As result, the main problem is that data instructions are constantly exchanged between memory (RAM) CPU clear form on bus. This may contain confidential like commercial software or private contents, which either end-user content provider willing to protect. paper describes...

This paper presents a Multi-Processor System-on-Chip platform which is capable of load balancing at run-time. The system purely distributed in the sense that each processor making decisions on its own, without having relying by any central unit. All management ensured very tiny preemptive RTOS (run-time operating system) running every mainly responsible for and distributing tasks among processing elements (PEs). goal such strategy to improve performance while ensuring scalability design. In...

This study describes the integration of thermally assisted switching magnetic random access memories (TAS-MRAMs) in field-programmable gate array (FPGA) design. The non-volatility is achieved through use tunnelling junctions (MTJs) an MRAM cell. A TAS scheme used to write data MTJ device, which helps reduce power consumption during a operation comparison with conventional writing devices. Furthermore, allows reducing both and configuration time required at each power-up circuit classical...