Multi-processor systems-on-chip (MPSoCs) are increasingly popular in embedded systems. Due to their complexity and huge design space explore for such systems, CAD tools frameworks customize MPSoCs mandatory. Some academic industrial available support bus-based MPSoCs, but few works target NoCs as underlying communication architecture. A framework targeting MPSoC customization must provide abstract models enable fast exploration, flexible application mapping strategies, all coupled features...

This article provides a comprehensive survey of pioneer and state-of-the-art localization algorithms based on the mobility network. The basic concepts task in wireless sensor network are revisited most common techniques suitable for random reviewed. compiles discusses relevant regarding mobile networks, focusing scenarios where nodes have no control over their hardware restrictions imposed, including recent advances learning-based solutions. It focuses presenting that do not rely human...

To cope with the dynamic workload of actual NoC-based MPSoCs, mechanisms are required to guarantee application requirements. Application mapping may drastically influence system performance and energy consumption, which can be crucial success (or failure) a product, even more for battery-powered embedded systems. In this context, current work presents an energy-aware task heuristic, was evaluated in real MPSoC platform. Results show that proposed heuristic reduces up 22.8% communication...

An important service in distributed systems, as multi-processors, is the ability to transmit multicast messages. Cache coherence protocols and parallel algorithms are examples of applications requiring To a message n targets, networks-on-chip without service, source router must identical Few works literature describe multicasting NoCs. The goal this work implement deadlock free routing algorithm for wormhole-switched mesh NoCs, enabling simultaneous dual-path algorithm, used multicomputers,...

A considerable number of NoC designs are available, focusing on different aspects this type communication infrastructure. Example relevant considered during design quality-of-service achievement, the choice synchronization method to employ between routers, power consumption reduction and application modules mapping. However, some choices common many if not most proposals: wormhole packet switching use virtual channels. This work dis-cusses trade-offs using circuit switching, arguing in favor...

This paper presents a Multi-Processor System-on-Chip platform which is capable of load balancing at run-time. The system purely distributed in the sense that each processor making decisions on its own, without having relying by any central unit. All management ensured very tiny preemptive RTOS (run-time operating system) running every mainly responsible for and distributing tasks among processing elements (PEs). goal such strategy to improve performance while ensuring scalability design. In...

The adoption of Networks-on-Chip (NoCs) as the communication infrastructure for complex integrated systems is a fact, and has been promoted by growing number processing elements in current MPSoCs. These are designed to execute several applications parallel, with different requirements distinct levels required quality service. To meet these restrictions, most designs customize MPSoC at design time, using specific NoC services adaptive routing algorithms, priorities, connections. However,...

For almost a decade now, Network on Chip (NoC) concepts have evolved to provide an interesting alternative more traditional intrachip communication architectures (e.g. shared busses) for the design of complex Systems (SoCs). A considerable number NoC proposals are available, focusing different sets optimization aspects, related specific classes applications. Each such application employs as part its underlying implementation infrastructure. Many mentioned aspects target results Quality...

Transaction level (TL) modeling is regarded today as the next step in direction of complex integrated circuits and systems design entry. This means that this definition evolves, automated synthesis tools will increasingly support it, allowing capture to start at a higher abstraction than today. work presents comparison traditional register transfer (RTL) transaction through implementation simple processor case study. SystemC language naturally supports hardware descriptions. The R8 was...

This paper proposes a novel strategy for optimizing resources in Multi-Processor Systems-on-Chip (MPSoC). The approach is based on using control-loop feedback mechanism to maximize the efficiency exploiting available such as CPU time, operating frequency, etc. Each Processing Element (PE) architecture equipped with frequency scaling module responsible tuning of processors at run-time according application requirements. Results show system's capability adapting disturbing conditions. For...

Task migration is a well-known strategy adopted in distributed systems for load balancing. but the adoption of such NoC-based MPSoC scarce literature. This paper proposes complete task protocol MPSoCs. The transfers code, data and context to another PE. presents communication ensure coherence messages delivery, heuristic compute new location, procedure inform position. Results evaluate cost using real (described synthesizable VHDL), demonstrating that migrate given has small impact system...

Multiprocessors systems on chip (MPSoCs) have become the de-facto standard in embedded systems. The use of Networks-on-chip (NoCs) provides to these platforms scalability and support for parallel transactions. computational power architectures enables simultaneous execution several applications, with different time constraints. However, as number applications executing simultaneously increases, performance such may be affected due resources sharing. To ensure requirements are met, mechanisms...

With the significant increase in number of processing elements NoC-based MPSoCs, communication becomes, increasingly, a critical resource for performance gains and quality-of-service (QoS) guarantees. The main gap observed MPSoCs literature is runtime adaptive techniques to meet QoS. In absence such techniques, system user must statically define, example, scheduling policy, priorities, switching mode applications. goal this paper investigate adaptation NoC resources, according QoS...

Transaction level (TL) modeling is regarded today as the next step in direction of complex integrated circuits and systems design entry. This means that this definition evolves, automated synthesis tools will increasingly support it, allowing capture to start at a higher abstraction than today. work presents comparison traditional register transfer (RTL) transaction through implementation simple processor case study. SystemC language naturally supports hardware descriptions. The R8 was...

Several NoC routing schemes proposals targeting overall performance optimization are available in the literature. However, such do not differentiate application flows. The goal here is to demonstrate that adaptive algorithms can be used flows with temporal constraints, enabling an enhanced degree of path exploration. main contribution this work expose algorithm at IP level. Results show gains latency, throughput and jitter for hotspot scenarios, minimal area overhead.

This paper explores the RSA (Rivest, Adi Shamir and Leonard Adleman) encryption/decryption performance using a scalable programmable approach with an improved processor architecture software implementation. The methodology gives new perspective when investigates design of custom hardware on flexible instruction set platform targeting embedded systems. consists stages at same time uses open-source big number library to execute operations up 4096-bit length. All optimizations are based...

The design of a Multiprocessor System-on-Chip (MPSoC) is complex task, including steps as application development, platform configuration, code generation, task mapping onto the and debugging. An integrated environment covering most these gap in literature. present work first details an MPSoC architecture, which supports execution distributed applications, operating system enabling multitask at each processing element. heterogeneous, due to support different processor architectures. Then,...

Networks-on-chip, or NoCs, are one communication architecture candidate to be used in present and future SoCs, due its scalability, reusability performance. The focus of this paper is the analysis IP models NoCs. Employing standard external interfaces, as OCP, recommended enable use NoCs by different core providers. second point related cores model. Two basic considered work: NUMA NORMA. goal work evaluate pros cons each model, terms network interface complexity, area

The use of NoCs in complex MPSoCs is a reality academic researches and industrial designs. A lot research effort has been conducted the last years NoC MPSoC designs, but few works address gap between infrastructure software applications. An important issue design QoS, since applications running such systems may have tight timing constraints, as video processing or fast communication protocols. This work bridges hardware/software gap, exploring integration low-level services into an...

The main goal of this work is to describe a scalable and reusable architecture useful for the construction Ethernet switches, named MOTIM. requirement MOTIM allow achieving low latency high throughput with generic structure that can be easily scaled. In order make scalable, its design based on use network chip (NoC), concept recently proposed enhancing SoC interconnect (Benini, 2002). NoCs stand as good compromise between silicon cost performance scalability, easing attain requirements....

As the number of cores and functionalities integrated in embedded devices increases, amount memory used on these also justifying development architectures presenting scalability, low energy consumption latency. To implement solutions, most works adopting NoC-based MPSoCs only employ basic communication services, such as send/receive, without exploring services NoCs can offer, for instance connection, priorities multicast communication. Multicast be to optimize cache coherence protocol,...

SoC design will require asynchronous techniques as the large parameter variations across chip impose challenges to control delays in clock networks and other global signals efficiently. Today's state-of-the-art SoCs contain an ever-growing number of IP cores, each which is immersed its independent domain. When core population increases minimum transistor size shrinks, it challenging keep all different domains synchronized die while maintaining considerable data bandwidth between them. One...

MPSoCs are largely used in embedded systems, allowing the design of complex systems within short time-to-market. The shift communication infrastructure, from buses to networks-on-chip (NoCs), adds new challenges. Standard directory-based cache coherence protocols represent a performance bottleneck due number transactions network, reducing and increasing energy consumption. State-of-the-art works investigate protocols, at abstract levels (e.g. TLM), optimize memory organization. Differently...

The emerging popularity of the Internet Everything makes security an urgent issue, as well need for speed to cipher and decipher any information, which is essential embedded devices. Unlike many works in this field, where propositions considering application specific integrated circuits (ASICs), coprocessors, field-programmable gate arrays (FPGAs) or software were presented alternatives raise efficiency execution, we addressed enhancement instruction set architecture (ISA) taking advantage a...