A5037580733- Interconnection Networks and Systems
- Real-Time Systems Scheduling
- Software-Defined Networks and 5G
- Embedded Systems Design Techniques
- Parkinson's Disease Mechanisms and Treatments
- Network Time Synchronization Technologies
- Advancements in PLL and VCO Technologies
- Reinforcement Learning in Robotics
- Evolutionary Algorithms and Applications
- Balance, Gait, and Falls Prevention
- Particle Accelerators and Free-Electron Lasers
- Particle accelerators and beam dynamics
- Vehicular Ad Hoc Networks (VANETs)
- Parallel Computing and Optimization Techniques
- Modular Robots and Swarm Intelligence
- Neurological disorders and treatments
- Advanced Memory and Neural Computing
- Neural Networks and Applications
- Radiation Effects in Electronics
- Robot Manipulation and Learning
- Architecture and Computational Design
- Neuroethics, Human Enhancement, Biomedical Innovations
- Complex Systems and Decision Making
- Robotic Path Planning Algorithms
- Brain Tumor Detection and Classification
Universitat Politècnica de Catalunya
2012-2023
Cornell University
2017-2019
Catalonian Research and Innovation Centre
2017-2019
Background Our group earlier developed a small monitoring device, which uses accelerometer measurements to accurately detect motor fluctuations in patients with Parkinson's (On and Off state) based on an algorithm that characterizes gait through the frequency content of strides. To further validate algorithm, we studied correlation its outputs section Unified Disease Rating Scale (UPDRS-III). Method Seventy-five suffering from disease were asked walk both On phase while wearing inertial...
The automotive industry is undergoing a deep revolution. With the race towards autonomous driving, amount of technologies, sensors and actuators that need to be integrated in vehicle increases exponentially. This imposes new great challenges electric/electronic (E/E) architecture and, especially, In-Vehicle Network (IVN). In this work, we analyze evolution IVNs, focus on main network processing platform them: Gateway (GW). We derive requirements Processing Platforms fulfilled by future GW...
Abstract Our research team previously developed an accelerometry-based device, which can be worn on the waist during daily life activities and detects occurrence of dyskinesia in patients with Parkinson’s disease. The goal this study was to analyze magnitude correlation between numeric output device algorithm results Unified Dyskinesia Rating Scale (UDysRS), administered by a physician. In study, 13 patients, who were symptomatic dyskinesias, monitored at home, for average period 30 minutes,...
Networks-on-Chip (NoC) is an emerging on-chip interconnection centric platform that influences modern high speed communication infrastructure to improve the performance of many-core System-on-Chip (SoCs) designs. The core each NoCs router involves arbiter and multiplier pairs need be carefully co-optimized in order achieve overall efficient implementation. Low transmission latency design one most important parameters NoC design. This paper uses parametric Verilog HDL implement designs...
In this work we introduce the concept of Elastic Queueing Engine (EQE) for Time Sensitive Networking (TSN) which is a new networking-optimized queueing strategy designed to maximize Quality Service (QoS) and usability resources in time sensitive networks. The proposed dynamic run-time adaptation queues network status exploits by introducing three degrees elasticity Hardware (HW), i.e., system able dynamically adapt events incoming traffic optimizing usage available resources. introduced EQE...
In this work authors present a Traffic Shaping Engine (TSE) intended for the next generation of Time Sensitive Networking (TSN) compliant Network/System on Chip (NoC/SoC) devices, targeting especially automotive industry. The TSE provides new layer abstraction that allows to integrate all TSN standards related traffic shaping are applicable In-Vehicle Networks (IVNs) according IEEE P802.1DG, providing common interface management shapers, independently algorithms in place. Hardware (HW)...
The paper presents a new solution for sampling rate conversion and processing of harmonic signals with known but possibly varying fundamental frequency. This problem is commonly found in particle accelerators, tracking the beam whose revolution frequency varies during acceleration ramp. It also common among many other fields such as speech music processing, removal mechanical noises, filtering biomedical recordings, active crack imaging, etc. key element proposed architecture Farrow-based...
In this work, authors introduce an innovative loopback strategy for In-Vehicle Network (IVN) processing in automotive gateway (GW) on Chip. The new proposed architecture is fully HW centric, and allows performing any IVN algorithms without intervention from the CPU. essence, adapting number of stages pipeline stage by betting centralization resources recirculating frames output to input when further are needed. It permits even select which send them depending required, optimizing thus...
In this work, authors present a Hardware (HW) based loopback strategy which is new paradigm in network processing, for HW efficient and cost-effective integration of Time Sensitive Networking (TSN) functionalities within automotive Gateways (GWs). This innovative architecture permits to manage the complexity TSN In-Vehicle Networks (IVNs) by reusing already existing resources GWs, interconnected such way that allows perform all required independently algorithms place. The proposed follows...
In this work, authors present a Hardware based strategy for IEEE802.1CB Network Reliability embedded in Automotive Gateways (GW). It is new approach HW efficient and cost-effective integration of Frame Replication Elimination (FRER) algorithm within automotive Network-on-Chip / System-on-Chip. essence, it architecture that permits to manage the complex In-Vehicle Networks. The FRER split into smaller functionalities which are allocated across different processing stages GW, maximizing device...
To enhance the performance of on-chip communications Globally Asynchronous Locally Synchronous Systems (GALS), a dynamic reconfigurable multi-synchronous router architecture is proposed to increase network on chip (NoC) efficiency by changing path communication link in runtime traffic situation. In order address GALS issues and bandwidth requirements, bidirectional NoC's developed it guarantees higher packet consumption rate, better utilization with lower delivery latency. All input/output...
Complex systems require an appropriate development methodology through the complete design lifecycle, from concept definition to system validation. In end, value and performance of a are limited by how well it can be tested validated. this work, authors present automatic framework for validation automotive Gateway controllers. The covers process, going test-case specification results delivery in fully way. relies on use standard Packet-CAPture (PCAP) files with frame traces, as mean...
Transient beam loading compensation schemes, such as One-Turn-FeedBack (OTFB), require synchronous processing (BSP). Swept clocks derived from the RF, and therefore harmonic to revolution frequency, are widely used in CERN synchrotrons; this simplifies implementation with energy ramping, where frequency changes. It is however not optimal for state-of-the-art digital hardware that prefers fixed clocks. An alternative swept clocking use of a deterministic protocol, example, White Rabbit (WR):...
Transient beam loading compensation schemes, such as One-Turn-FeedBack (OTFB), require synchronous processing (BSP). Swept clocks derived from the RF, and therefore harmonic to revolution frequency, are widely used in CERN synchrotrons; this simplifies implementation with energy ramping, where frequency changes. It is however not optimal for state-of-the-art digital hardware that prefers fixed clocks. An alternative swept clocking use of a deterministic protocol, example White Rabbit (WR):...
The clock distribution within Chip-Multiprocessors(CPMs) and System-on-chips (SoCs) come to be difficult as the number of processing elements increasing communication between those components are becoming even more critical. In recent years, researchers proposed Globally Synchronous Locally (GALS) clocking scheme reduce skew, power, energy consumption in CPMs SoCs. this paper we have demonstrated dynamic depth multi-synchronous first-in first-out (FIFO) buffer which is useful for...
Recently Multi-core Globally Asynchronous Locally Synchronous(GALS) architecture emerged as the de facto to solution satisfy performance requirement of mainly modern embedded applications. Due scalability, flexibility, and high bandwidth properties, Network-on-chip (NoC) technique has been proposed a promising for communication-centric platform. The rapid introduction NoC multi-core GALS requires proper Network-Interface (NI) design interface two different IP blocks via network routers...
Evolution plays an increasingly important role in enabling autonomous robots to survive a partly uncertain and changing environment. Yet the growing success of domestic field robotics shows importance design framework. The methodology presented here explicitly addresses evolution integration. Mimicking biological nervous system's network neurons, comparable low-level ubiquitous element is developed, called imbalance element. This element's model stems from comparing diverse behavior...