- Electronic Packaging and Soldering Technologies
- 3D IC and TSV technologies
- Epoxy Resin Curing Processes
- Injection Molding Process and Properties
- Mechanical Behavior of Composites
- Heat Transfer and Optimization
- Material Properties and Processing
- Semiconductor materials and devices
- Copper Interconnects and Reliability
- Additive Manufacturing and 3D Printing Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Electromagnetic Compatibility and Noise Suppression
- Polymer composites and self-healing
- Fluid Dynamics and Thin Films
- Flame retardant materials and properties
- Microbial Applications in Construction Materials
- Electrostatic Discharge in Electronics
- Advanced Measurement and Metrology Techniques
- VLSI and Analog Circuit Testing
- Advanced Memory and Neural Computing
- Piezoelectric Actuators and Control
- Advanced machining processes and optimization
- Metal Forming Simulation Techniques
- VLSI and FPGA Design Techniques
National Kaohsiung University of Science and Technology
2023
Taiwan Semiconductor Manufacturing Company (Taiwan)
2012-2023
National Tsing Hua University
2013-2020
in this paper, we demonstrate a high density heterogeneous large package using RDL interposer with six interconnection layers. Four Si chiplets and two HBM modules are connected fine pitch copper lines to deliver complete system-in-package solution for performance computation. The multilayer interconnections provide excellent design flexibility optimize signal, power, ground planes. has generic structural advantages integrity bump joint reliability, which allows further scaling up of size...
Heterogeneous integration with advanced packaging has recently been the subject of intensive discussion and development to pursue optimum electronic system performance. The concept miniaturized systems is particularly important for applications such as wearable portable devices, demands more integrated functionality, better performance smaller form factors persist. In this paper, we reveal a new multilayer 3D fan-out stacking approach an ultra-thin 6-layer stacked package low warpage....
Organic interposer (CoWoS®-R) is one of the most promising heterogeneous integration platform solutions for high-speed and artificial intelligence applications. Components such as chiplets, high-bandwidth memory, passives can be integrated into an organic with excellent yield reliability. This paper presents reliability results advanced packages. Multiple redistribution layers (RDLs) form effective stress buffer reducing induced in C4 joint its underfill from mismatch between top dies...
Two-phase immersion cooling is a promising technology for 2.5D/3D heterogeneous integration packages 5G and AI applications. For the first time, this study applies two-phase to chip on wafer substrate (CoWoS) HPC package with thermal design power (TDP) of up 900 W. Two different boiler designs integrated CoWoS are considered consisting porous surface structures such as powder or mesh deposited solid copper base vapor chamber base, respectively. The characteristics two examined compared...
Molded underfill (MUF) is an essential component in ultra-thin flip chip packages to ensure their long-term reliability and mechanical integrity. However, the warpage evolution of package during curing process MUF has a critical effect on both SMT yield reliability. Therefore, thorough understanding physical behavior under essential. The present study therefore successfully establishes novel modeling approach based finite element method predict final scale (fcCSP) accordance with chemical...
The viscoelastic behavior of the molding compound in fine pitch encapsulated electronic packages has a significant impact on component warpage and SMT assembly reliability. This is particularly true for thin or ultra-thin (such as fan-out) used mobile handsets tablets, where process-induced exacerbated by larger volume higher density Cu trace layout. To ensure good process yield long term reliability, relaxation during wafer should be specially addressed optimized with effects cure-dependent...
With HPC devices continue to scale up for higher power and density, thermal dissipation management IC packages are becoming an important issue. This paper presents the solution evolution at package level system level, that drives towards more advanced TIM1 liquid or immersion cooling solution. Thermal-aware device floorplan, critical enable application
In order to efficiently optimize the structure and process of thin packages, it is crucial accurately predict warpage packages during in-molding post-mold curing (PMC) processes. this paper, we describe an integrated modeling approach, which takes both viscoelastic chemical shrinkage behaviors into account for molded underfill process. The time-domain properties are included in finite-element (FE) model. simulation results good agreement with measured 3D contour values by Shadow Moiré...
The viscoelastic behavior of the molded underfill (MUF) in fine pitch encapsulated electronic package has a significant impact on warpage and SMT assembly reliability. To ensure high reliable solder joint yield, evolution during reflow is critical should be optimized. This study presents an integrated process modeling approach with finite-element method to predict based time-domain MUF material its chemical shrinkage properties. predicted not only shows good agreement experimental data...
Due to the significant volume change of molding compounds during assembly processes, warpage is top issue be overcome in application fan-out wafer form. Minimizing process, though challenging, essential for ensuring good process yields. In this paper, we propose a predictive modeling approach accurately address evolution and effectively mitigate by optimizing conditions. This establishes viscoelastic-based material model accounting cure-dependent viscoelastic relaxation behavior compound....
The molded underfill (MUF) offers many unique advantages, including lower material costs, higher throughput, and excellent reliability for flip-chip chip scale packages (fcCSP) fan-out packages. assembly process yield of these are significantly influenced by the warpage behaviors MUF. We develop an integrated modeling approach incorporated with real-time chemical shrinkage cure-dependent viscoelastic constitutive model prediction. shrinkage, kinetics viscoelasticity measured using...
Three-dimensional (3D) fanout package stacking offers new levels of performance, high-density integration, and form factor advantages. Known-good packages are stacked, the vertical connection is built through Cu pillars in molding area solder bumps. Compared to existing TSV-based 3D integrated circuits (3DIC) technology, this solution reduces thermal crosstalk when integrating devices different die sizes. Fanout potentially provides a cost-effective platform for highly flexible heterogeneous...
Board level reliability during drop impact is a major concern for electronic packages. The force generated as the casing strikes ground can cause device failures in handheld products. full testing procedure costly and time-consuming due to complex sample preparation test set-up procedures. Failure analysis also requires significant manpower conduct. Therefore, an modeling method predict results of board drops highly desirable. We propose dynamic approach describe transient response package...
In order to ensure good performance and long-term reliability of fan-out package, the interfacial strength Underfill (UF) polymer (PM) lamination plays an important role because physical electrical requirement. Accordingly, present study presents a combined experimental finite element modeling approach for quantitatively determining adhesive UF-PM structures. proposed approach, four points bending (FPB) testing is used evaluate adhesion between UF-PM. The test results are determine critical...
Self-align nitride (SAN) logic NVM cell has been successfully demonstrated in 28nm CMOS technology with high-k gate dielectric layer and metal WL for coupling. This work proposed a new method program erase of the SAN cells, when length spacing scales aggressively to 40nm 70nm, respectively. Reliable 2-bit per operation by local hot hole injection controlled WLs are future applications high density arrays.
Underfill (UF) polymer (PM) structures are becoming increasingly popular in fan-out packages because they exhibit several advantages, such as protection from mechanical stress and package- to-system electrical thermal conductivity. The laminate integrity of UF-PM interfaces plays a crucial role determining package performance long-term reliability. In this study, we presented fracture-mechanics-based experimental method finite element to quantitatively determine the interfacial adhesive UF...
Three-dimensional (3D) fanout package stacking offers new levels of performance, high-density integration, and form factor advantages. Known-good packages are stacked, the vertical connection is built through Cu pillars in molding area solder bumps. Compared to existing TSV-based 3D integrated circuits (3DIC) technology, this solution reduces thermal crosstalk when integrating devices different die sizes. Fanout potentially provides a cost-effective platform for highly flexible heterogeneous...
Warpage has always been an important issue in electronic packaging, especially for fan-out and flip-chip chip scale packages (fcCSP). The molded underfill encapsulation plays a key role warpage control. It is critical to establish fundamental understanding of the properties cure-induced shrinkage viscoelasticity, effects pressure, temperature, volume variation, degree cure on package warpage.In this study, cure-dependent viscoelasticity are carefully characterized during in-molding post...
Warpage control of an ultrathin package is critical in the semiconductor industry because large volume molded underfill (MUF) encapsulated such packages and low stiffness entire structure. The viscoelastic relaxation behavior that observed during MUF curing process results a major warpage change thus should be investigated. First, material model cure-dependent viscoelasticity time domain kinetics were successfully established based on characterization results. Then, finite-element (FE)...
With HPC devices continue to scale up for higher power and density, thermal dissipation management IC packages are becoming an important issue. This paper presents the solution evolution at package level system level, that drives towards more advanced TIM1 liquid or immersion cooling solution. Thermal-aware device floorplan, critical enable application.
Copper/polymer structure is a prominent part in wafer level package (WLP) for electrical and thermal connectivity of package-to-system. Due to higher density Cu redistribution layer (RDL) advanced packages, the robustness Cu/polymer such as adhesion becoming more critical than ever ensure long term reliability. In this paper, characterization methodologies interface are investigated. Compared stud-pull test which widely used industry, fracture toughness characterized by four-point bending...
With the increasing package size and power consumption of HPC applications, controlling thermal performance impact from package-to-system interaction (PSI) in 2.5D/3D chiplet or heterogenous integration packages is crucial for ensuring their long-term reliability typical operating environments. The present study thus conducts an experimental numerical analysis PSI a large lidless type 2.5D heterogeneous system with fanout area more than twice reticle. focuses particularly on effects heatsink...