This study describes a strategy for developing ultra-high-responsivity broadband Si-based photodetectors (PDs) using ZnO nanorod arrays (NRAs). The NRAs grown by low-temperature hydrothermal method with large growth area and high rate absorb the photons effectively in UV region provide refractive index matching between Si air long-wavelength region, leading to 3 2 orders of magnitude increase responsivity metal-semiconductor-metal PDs visible/NIR regions, respectively. Significantly enhanced...

We demonstrate solar-blind photodetectors (PDs) by employing AlN thin films on Si(100) substrates with excellent temperature tolerance and radiation hardness. Even at a bias higher than 200 V the PDs Si show dark current as low ~ 1 nA. The working is up to 300°C 10(13) cm(-2) of 2-MeV proton fluences for metal-semiconductor-metal (MSM) PDs. Moreover, photoresponse time fast 110 ms (the rise time) 80 fall 5 bias. results that MSM hold high potential in next-generation deep ultraviolet use...

This work demonstrates the high-temperature operation of metal-semiconductor-metal (MSM) photodetectors (PDs) up to 450 °C using lightly Al-doped epitaxial 4H-SiC thin films. The responsivity PDs under 325-nm illumination is 0.0305 A/W at 20-V bias room temperature. photocurrentto-dark-current ratio SiC MSM as high 1.3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> 25 and 0.62 °C. rise/fall time increased slightly from 594 μs/684...

Highly c-axis oriented heteroepitaxial aluminum nitride (AlN) films were grown on epitaxial cubic silicon carbide (3C–SiC) layers Si (100) substrates using alternating current reactive magnetron sputtering at temperatures between approximately 300–450 °C. The AlN characterized by x-ray diffraction, scanning electron microscope, and transmission microscopy. A two-port surface acoustic wave device was fabricated the AlN/3C–SiC/Si composite structure, an expected Rayleigh mode exhibited a high...

Single-crystalline Er-doped ZnO nanorod arrays (NRAs) on Ag island films with appropriate annealing show a promising enhancement of 1540 nm emission for optical communication. The enhanced NRAs is attributed to the deep level host. In an effort enhance pump Er3+ at in NRAs, surface plasmon coupling and increase states were carried out via high-temperature annealing. This study points effective methods emission, demonstrating that islands have potential application communications.

This work demonstrates high-temperature operation of metal-semiconductor-metal photodetectors (MSM PDs) using low-temperature, ion beam-assisted deposition nanocrystalline SiC thin films and hydrothermal synthesis ZnO nanorod arrays (NRAs). Due to the incorporation NRAs, photo-to-dark current ratio MSM PDs is increased from 4.9 13.3 at 25 °C 7.6 200 °C. The enhancement in sensitivity suggests that NRAs could serve as an effective antireflective layer guide more light into PDs. was confirmed...

The epitaxial growth of 3C-SiC films on Si(100) substrates is demonstrated using a two-step chemical vapor deposition (CVD) process. A thin (50 nm) SiC buffer layer grown at 925 °C 1,3-disilabutane shown to enable the high crystalline quality film methyltrichlorosilane 1200 °C. ability deposit high-quality traced suppression void defects and improvement in adhesion obtained by low temperature.

During an at-speed scan-based test, excessive capture power may cause significant current demand, resulting in the IR-drop problem and unnecessary yield loss. Many methods address this by reducing switching activities of power-risky patterns. These not be efficient when number patterns is large or some require extremely high power. In paper, we propose discarding all starting with power-safe only. Our test generation procedure includes two processes, namely, pattern refinement low-power...

The conventional output compaction methods based on XOR-networks and/or linear feedback shift registers may suffer from the problems of aliasing, unknown-values, poor diagnosability. In this paper, we present an alternative method called output-bit-selection to address test problem. By observing only a subset responses, can effectively deal with all above-mentioned problems. Efficient algorithms that identify near optimum subsets bits cover detectable faults in very large circuits are...

This paper proposes an efficient diagnosis-aware ATPG method that can quickly identify equivalent-fault pairs and generate diagnosis patterns for nonequivalent-fault pairs, where (non)equivalent-fault pair contains two stuck-at faults are (not) equivalent. A novel fault injection is developed which allows one to embed all undistinguished by the conventional test into a circuit model with only copy of original circuit. Each be processed transformed dealt invoking ordinary tool just once. High...

Output selection is a recently proposed test response compaction method, where only subset of output bits selected for observation. It can achieve zero aliasing, full X-tolerance, and high diagnosability. One critical issue how to implement the hardware. In this paper, we present counter-based scheme that employs counter multiplexer, hence involving very small area overhead simple control. The ATPG-independent thus easily be incorporated into typical design flow. Two efficient algorithms are...

Test-per-clock BIST scheme has the advantages of very short test application time and small data volume. However, conventionally this needs an extra parallel response monitor for analysis that may lead to large area overhead. This paper presents a new test-per-clock method can perform both pattern generation compression concurrently in same LFSR-based design so as reduce Furthermore, some internal nets are employed two ways during help volume: 1) observation points enhance fault...

This paper proposes a new test-per-clock BIST method that attempts to minimize the test sequence length and data volume simultaneously. An efficient LFSR reseeding algorithm is developed by which each determined seed together with its derived patterns can detect maximum number of so far undetected faults. During determination process an adaptive X-filling first employed generate set candidate for pattern embedding. The then derives solution embed multiple at one time as seeds. To shorten...

Mixed-mode BIST enhances test efficiency of digital circuits by combining the advantages both pseudo-random and deterministic patterns. In order to apply patterns, most traditional methods need store some data in external testers or on-chip memory. this paper we present a novel mixed-mode technique which all patterns can be generated on chip real time thus requiring no storage device. By appropriately connecting internal nets circuit under inputs circuit, together with set scheme reach full...

Twisted-ring-counters (TRCs) have been used as built-in test pattern generators for high-performance circuits due to their small area overhead, low performance impact and simple control circuitry. However, previous work based on a single, fixed-order TRC often requires long time achieve high fault coverage large storage space store required data seeds. In this paper, novel programmable multiple-TRC-based on-chip generation scheme is proposed minimize both the volume. The scan path of circuit...

The heteroepitaxial growth of cubic silicon carbide (3C-SiC) films on AlN/Si(100) substrates is demonstrated using a modified precursor feeding procedure chemical vapor deposition process. A thin (150 nm) SiC buffer layer formed during the temperature ramp from 600 to in presence methyltrichlorosilane and hydrogen gas. deposited 3C-SiC film exhibits sharp Raman transverse optical peak, strong X-ray diffraction intensity for SiC(111) an atomically abrupt SiC/AlN interface. These...

In this paper, we demonstrate the stable operation of integrated 4H-silicon carbide (SiC) diode bridge rectifier circuits at high temperature up to 773 K for first time. The turn-on voltages fabricated 4H-SiC pn are 2.6 V and 1.4 room K, respectively, with a low shifting rate 2.2 mV/K. integration circuit was achieved contact interconnect metallization technique temperature. demonstration extremely brings promising applications in harsh environment electronics sensing.

The growth of cubic silicon carbide films with tunable porosity is demonstrated on Si(100) using a single precursor, methyltrichlorosilane, chemical vapor deposition process in the temperature range 950–1200 °C. pore size varies from 250 nm to 2 μm and it controlled by details hydrogen introduction during substrate heating stage. It proposed that outdiffusion combined chloride production adsorption surface at high may be responsible for porous thus produced.

Recently internal-response-based BIST techniques are proposed. By using internal circuit responses to directly generate test patterns, these can significantly reduce or even eliminate storage requirement for data. For techniques, appropriate routing of the nets circuitry is crucial minimizing required area overhead and induced performance impact. In this paper, an efficient net sharing algorithm together with special response decompressor hardware proposed minimize total number scheme....

This work demonstrates a method to develop high temperature metal-semiconductor-metal photodetectors using low-temperature, ion beam assisted deposition of nanocrystalline silicon carbide (SiC) and hydrothermal synthesis zinc oxide (ZnO) nanorod arrays. Due incorporation ZnO arrays, the photo-to-dark current ratio Au/nanocrystalline SiC is increased from 4.9 13.3 at 25°C 4.85 7.57 200°C. The results, suggest that arrays could serve as an antireflection layers guide more light into...

Highly c-axis oriented aluminum nitride (AIN) films were grown on epitaxial cubic silicon carbide (3C-SiC) layers Si (100) substrates using alternating current (AC) reactive magnetron sputtering at temperatures between 300 °C to 450 °C. The AIN thin characterized by X-ray diffraction, scanning electron microscope, and transmission microscopy. Two-port surface acoustic wave (SAW) devices fabricated the AIN/3C-SiC/Si layered structure. SAW propagation properties in AlN/3C-SiC/Si structure...

Output-bit selection is a recently proposed test-response compaction approach that can effectively deal with aliasing, unknown-value, and low-diagnosis problems. This has been implemented using single counter multiplexer without considering unknown values. Also, such an implementation may require the application of pattern multiple times in order to observe all selected responses. In this paper, we present multiple-counter-based architecture new algorithm avoid most unknown-values yet...