The degradation of AlGaN/AlN/GaN high electron mobility transistors due to 1.8-MeV proton irradiation was measured at fluences up 3/spl times/10/sup 15/ cm/sup -2/. devices have much higher than AlGaN/GaN devices, but they possess similarly radiation tolerance, exhibiting little 1/spl 14/ Decreased sheet carrier increased scattering and decreased density removal are the primary damage mechanisms. device is observed as a decrease in maximum transconductance, an increase threshold voltage,...

Large thermal mismatch stress can be introduced in 3D-Integration structures employing Through-Silicon-Via (TSV). The distribution silicon and interconnect is affected by the via diameter layout geometry. TSV induced changes mobility ultimately alters device performance. performance change differs nand p- a function of distance to TSV. In addition, acts on barrier layer, landing pad, interconnects, dielectrics. interactions with defects may lead crack nucleation growth, compromise structure...

1.8 MeV proton radiation-induced degradation in high electron mobility transistors with Si-doped Al/sub x/Ga/sub 1-x/N and thick GaN cap layers is studied up to a fluence of 1/spl times/10/sup 15/ protons/cm/sup 2/. The layer reduces sheet charge modulation induced by the surface states, as it electrostatically separates active device from surface, thereby enhancing performance. devices exhibit good tolerance 10/sup 14/ 2/, displacement damage being primary mechanism. Charged defect centers...

Abstract The parametric surrogate models for partial differential equations (PDEs) are a necessary component many applications in computational sciences, and the convolutional neural networks (CNNs) have proven to be an excellent tool generate these surrogates when fields present. CNNs commonly trained on labeled data based one-to-one sets of parameter-input PDE-output fields. Recently, residual-based deep physics-informed network (DCPINN) solvers PDEs been proposed build without need data....

We have characterized high-electron mobility transistors and corresponding unprocessed material as a function of 1.8 MeV proton fluence. Electrical data shows degradation the electrical contacts at low fluences (10/sup 11/-10/sup 14/ p/sup +//cm/sup 2/) channel properties for higher fluences. In conjunction with data, cathodoluminescence secondary-ion mass spectrometry results suggest mechanisms fluence degradation.

Proton irradiation decreases the doping concentration and increases ideality factor series resistance, but has very little effect on Schottky barrier height in n-Gallium nitride diodes. 1.0-MeV protons cause greater degradation than 1.8-MeV because of their higher nonionizing energy loss. The displacement damage recovers during annealing. Comparison between diodes high electron-mobility transistors suggests that both types devices is predominantly due to carrier removal mobility caused by...

Thermo‐mechanical stresses are introduced in three dimensional integration structures employing TSVs during fabrication process. Stress analysis is required order to manage the stress related performance and reliability issues 3D TSV stacks. The parasitic parameters need be examined at same time for system design optimization. In this paper, TCAD methodologies process simulation, modeling demonstrated. mechanical impact on device structural various materials geometries examined. their...

The elastic anisotropy of copper through-silicon vias (TSVs) and its impact on performance reliability in 3-D integrated structures is examined. Copper TSVs exhibit significant amount anisotropy, particularly for with very small diameters. manifests itself terms different Young's moduli directions results orientation-dependent stress distributions. measured, the stress-induced mobility variation structural examined using an advanced technology computer-aided design simulator. It observed...

Copper plastic deformation and liner viscoelastic flow effects on performance reliability are studied for TSV-middle backside TSV-last fabrication processes. Incremental plasticity model with nonlinear hardening Maxwell viscoelasticity employed to characterize TSV copper dielectrics material behaviors. The parameters chosen match experimental data. It is found that both in affect the trade-off between keep-out-zone (KOZ) size extrusion. process generates less residual stresses mobility...

A decrease in the oxide-charge trapping efficiency of Al- and TaSi-Al-gate MOS capacitors with oxide thicknesses ranging from 33 to 100 nm was observed after more than 14 years room-temperature storage. The can be reduced or even eliminated Al-gate (and a lesser degree TaSi-Al) devices by baking them at temperatures up /spl sim/200 deg/C. This change aged-device radiation response is largely independent time, least for 1-18 h bakes. Poly-Si gate processed stored under similar conditions show...

A new methodology to bridge package and silicon domain simulations is demonstrated using a data file facilitate stress information exchange. The flow integration uses equivalent conditions replace sensitive process parameterized modules minimize user interventions for 3D IC simulations.

We report the first application of second-harmonic generation (SHG) measurements for characterization X-ray radiation damage in Si/SiO/sub 2/ structures. The main advantage this experimental technique is that it noninvasive, contactless, and sensitive to electric field at interface. Interaction intense 800 nm femtosecond laser pulses with structures results electron-hole pair creation Si, multiphoton carrier injection generation. time-dependent (doubled frequency) signal a measure dynamic...

A novel simulation approach is developed to examine the stress evolution in chip-to-package interconnect structures during sequential IC Backend processes followed by packaging / assembly operation. Packaging induced near-bump and BEOL level models examined using multi-level FEA methodology. Likewise, process stresses analyzed a that looks into of structure as each metal-dielectric layer being patterned. Finally, cumulative impact on demonstrate significance this performing "design...

The effects of copper permanent deformation during thermal cycles in backside through-silicon via (TSV)-last fabrication process are studied using an advanced 3-D simulator. plasticity and creep model parameters chosen to match experimental data. Two sets different TSV configurations back end line (BEOL) layouts utilized examine reliability, BEOL front-end device performance after postplating excursion. results indicate that the affects stress distributions for TSV-last process....

Deep sub-micron technologies employ dummy metal fills in the interconnect layouts with adequate pre-CMP pattern density distribution to achieve post-CMP planarization. Dummy placement has a significant impact on parasitic capacitance and it also alters mechanical stresses structure. The combined effects of are examined this study. is found be strongly correlated fill pattern. Some patterns studied here result improved parameters but lead deterioration local stress fields that reliability...

Copper plasticity effects in TSV middle and backside last integration flows are analyzed using an advanced 3D TCAD simulator with model parameters calibrated to match experimental data. In this work, a low thermal budget flow is considered. contrast the flow, studied here exhibits insignificant pumping, M1 metal thinning or resistance increase. The difference residual stress profiles BEOL structure for processes indicates that process sequence must be optimized order minimize reliability...

Reliability analysis for three bumping configurations is performed under typical chip package interaction. A sequential submodeling technique employed to capture stress evolution during entire assembly process. Mechanical stresses are assessed in various regions around bumps determine the optimal scheme with minimal reliability risk. Underfill material property impact on also examined. This study provides important guidelines design robust fine-tuned properties.

This paper demonstrates a TCAD based stress modeling approach for analyzing thermal mechanical evolution and evaluating induced performance reliability effects in 3D IC structures. A typical fabrication assembly process is examined. It observed that various TSV micro-bump design parameters need to be optimized order minimize the impact fabricate robust copper anisotropy effect also investigated. Strategies device variation improve structural are discussed.

In the above titled paper (ibid., vol. 12, no. 2, pp. 225-232, June 2012), Fig. 1 did not appear correctly. The corrected is presented here.

Abstract Distinct temperature and process dependent deformation behaviors under packaging cycles are characterized for various materials. Substrate underfill deformations described using Maxwell viscoelasticity model. Solder bump is represented by incremental plasticity Anisotropic in silicon orthotropic substrate also considered. The material effects on stress evolutions during fabrication chip package interaction (CPI) analyzed a large structure. Complex geometries spread over range of...