A5045809760- Advancements in PLL and VCO Technologies
- Semiconductor materials and devices
- Radio Frequency Integrated Circuit Design
- VLSI and Analog Circuit Testing
- Analog and Mixed-Signal Circuit Design
- Photonic and Optical Devices
- Low-power high-performance VLSI design
- Semiconductor Lasers and Optical Devices
- Optical Network Technologies
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Advancements in Semiconductor Devices and Circuit Design
- Embedded Systems Design Techniques
- Electromagnetic Compatibility and Noise Suppression
- Integrated Circuits and Semiconductor Failure Analysis
- Cellular Automata and Applications
- Error Correcting Code Techniques
- Wireless Body Area Networks
- 3D IC and TSV technologies
- Parallel Computing and Optimization Techniques
- VLSI and FPGA Design Techniques
- Neuroscience and Neural Engineering
- Molecular Communication and Nanonetworks
- Radiation Effects in Electronics
- Semiconductor Quantum Structures and Devices
Kwangwoon University
2021-2025
Samsung (South Korea)
2023
SK Group (South Korea)
2019-2021
Seoul National University
2013-2020
As the dynamic random-access memory (DRAM) process is being scaled down, sensing margin of bit-line sense amplifier (BLSA) decreasing. This leads to failure due offset and long time BLSA. To address this issue, various compensation methods technologies that reduce have been proposed. However, these still exhibit times in low-power large-capacity with low supply voltage high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math...
A single-ended four-level pulse-amplitude modulation (PAM-4) transmitter (TX) for memory interfaces achieves high signal integrity by combining an impedance-matched PAM-4 driver with a three-point ZQ calibration scheme. This improves linearity allowing the to compensate its impedance variation caused change in drain-source voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> ) suit four output levels considering both TX and...
The demand for high-bandwidth data communication in various data-centric applications has increased significantly. It requires many repetitive transfers between processing units and off-chip memories, owing to the limited memory I/O bandwidth. This results a deterioration system throughput energy efficiency. Therefore, an energy-efficient interface is required. NRZ signaling [1], [2] commonly used interfaces; however, it difficult increase bandwidth beyond certain point on-chip limitations....
For the first time, we demonstrated experimentally 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> single-gated IGZO-VCT, monolithically stacked on top of core/peripheral transistors without wafer bonding process for sub-10nm DRAM. Sufficiently low leakage current (I <inf xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> ) <1 fA/cell, subthreshold swing (SS) 164 mV/dec and V xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> -1.73...
A quadrature clock corrector uses relaxation oscillators to detect duty-cycle and phase errors by transforming them into pairs of frequencies, which are then digitized compared. It achieves good detection accuracy can a wide range errors. The prototype is implemented in 55-nm CMOS process with supply voltage 1.2 V occupies an area 0.003 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . experimental results show that the operation from...
In multi-lane interfaces using single-ended signaling such as memory interfaces, far-end crosstalk (FEXT) noise of the aggressor signal severely degrades integrity victim signal. A circuit for cancellation (XTC) can reduce FEXT noise. However, channel spacing makes flight time difference between forward and signals. As a result, residual remain. To further minimize FEXT, this study proposes an XTC method to adjust amplitude timing independently. The is adjusted according passive element's...
Phase and amplitude emphasis are combined in a 2.1-Gb/s 12-channel transmitter for ultra-high definition (UHD) intra-panel interface. The performs phase within the final 2:1 stage of its 20:1 serializer. This reduces datadependent jitter (DDJ) without increasing IO capacitance by making timing bit transitions depend on previous data. We have also proved compensation effect this mathematical analysis. low-voltage differential signaling (LVDS) driver can accommodate 300mV variation common-mode...
We combine 2-tap feed-forward amplitude equalization with phase by 4-tap integrated pulse-width modulation. In a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</sub> -terminated transmitter, is selected for pull-up data transmission, and pull-down the strength of can be controlled depending on channel losses. This combines energy efficiency equalization. A prototype quarter-rate transmitter memory interfaces, fabricated in 65nm CMOS...
This brief presents a 12.8-Gb/s quarter-rate transmitter for DDR interfaces. The 4:1 serialization required in is performed by an overlapped multiplexing driver containing four unit drivers. Two of drivers output two identical 1UI full-rate DQ signals simultaneously and these are merged while they perform final serialization. reduces the I/O capacitance. Correct timing this process maintained adaptive alignment phases clock signal. Implemented 55-nm CMOS technology, single-ended swing...
In this paper, a 20Gb/s dual-mode four-level pulse amplitude modulation (PAM4)/non-return-to-zero (NRZ) single-ended voltage-mode transmitter is proposed. Its output drivers are composed of 60 basic source-series terminated (SST) driver units and 12 additional pull-up (PU) units. The PU used to reduce the eye height difference between four levels PAM4. Implemented in 65nm CMOS technology, active area 0.06mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
In asymmetric memory systems, the pull-up and pull-down data from channel can have different amounts of inter-symbol interference (ISI), so they cannot be fully corrected by an equalizer which uses a single tap weight. We introduce receiver-side single-ended 1-tap decision-feedback (DFE) with weight selection multiplexer, allows application to each direction value transition. Implemented in 55-nm CMOS technology, our DFE compensated for ISI 10.4-Gb/s signal insertion loss -8.3 dB, leading...
The demand for high-performance graphics systems used artificial intelligence continues to grow; this trend requires achieve ever higher bandwidths. Enabling GDDR6 DRAM data rates beyond 18Gb/s/pin [1] identifying and solving factors that affect the speed of a memory interface. Prior studies have showed interface is vulnerable from signal integrity (SI) power (PI) perspective, since it based on parallel using single-ended signaling. Furthermore, circuit schemes mitigate process, voltage,...
The demand for high-performance graphics systems used artificial intelligence, cloud game, and virtual reality continues to grow; this trend requires achieve ever higher bandwidths. This article proposes a GDDR6 dynamic random access memory (DRAM) with half-rate clocking architecture optimized receiver transmitter improve high-speed operation. Furthermore, adopts staggered PAD using the redistribution layer (RDL) reduce distance four PADs; it enables mitigation of bandwidth limitation...
A 266–2133 MHz phase shifter is proposed for LPDDR4X interface, utilising an all‐digital delay‐locked loop (DLL) and a triangular‐modulated interpolator (PI) to improve the jitter linearity. The DLL consists of two kinds DLLs: global assist fast locking; local which uses adaptive‐window detector folded delay line reduce PI clock waveform achieve good linearity over wide frequency range. prototype chip implemented in 65 nm CMOS process. measured 3.08 ps rms /19.93 pp at 2133 MHz. differential...
Duty-cycle distortion may occur due to variations in the process, voltage, and temperature, or if clock signal passes through buffers. To compensate duty-cycle distortion, a digital corrector (DCC) with counter-based half-cycle delay line (HCDL) is introduced. The HCDL of conventional edge combiner-type DCC requires large area makes unsuitable for applications that operate at wide-range frequency, such as memory ADC interfaces. proposed reduces silicon cost by repeating while maintaining...
A single-ended transmitter achieves low power consumption with an integrated voltage modulation (IVM) scheme for memory interfaces. The preserves the advantages of ground (VSS)-terminated signaling by consuming no static when transmitting logic-0s before last bit consecutive (CLZs). All intersymbol interference (ISI) accumulated during CLZs is compensated at once proposed IVM, which provides unit interval (UI) spaced compensation period logic-0. equalization, combining four-tap IVM and...
In this paper, we propose a time-to-digital converter (TDC) that uses multi-phase cyclic Vernier delay line (VDL) to achieve the high-resolution and wide-dynamic range. Its control voltages are provided by two phase-locked loops (PLLs) compensate for process ambient variations. The PLLs share single reference clock have different frequency-division ratios. It also improves resolution of TDC. A prototype chip, designed fabricated in 0.18μm CMOS technology with an active area 0.40mm <sup...
A 4266Mb/s/pin LPDDR4 interface with an asynchronous feedback continuous-time linear equalizer (AF-CTLE) and adaptive 3-step eye detection algorithm for memory controller is presented. The AF-CTLE removes the glitch of DQS without training by applying offset larger than noise, improves read margin operating as a decision in DQ path. reduces power consumption black-out time initialization sequence retraining comparison to 2-D full scanning. prototype chip was implemented 65-nm CMOS process...
The increasing data rate of serial links makes it difficult to match timing constraints serializers in transmitters. Delay compensation clock buffers can alleviate this issue by matching the between and clock. However, these consume significant power become sources noise transmitter output. problem is more serious for other than 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> :1, using only :1 serializer could be a limitation on system...
This brief presents a 9Gb/s transmitter for intra-panel interfaces, with dual-loop calibration and 2D binary-segmented driver. The during the training period compensates output variations in operating conditions such as supply voltage reference current. driver provides wide range high resolution characteristics, independent adjustments VOD, VCM FFE strength while maintaining signal integrity. reduces power consumption by optimizing channel. A prototype chip, fabricated 55nm CMOS process,...