A5024718349- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- Photonic and Optical Devices
- Analog and Mixed-Signal Circuit Design
- Semiconductor Lasers and Optical Devices
- VLSI and Analog Circuit Testing
- Electromagnetic Compatibility and Noise Suppression
- Semiconductor materials and devices
- 3D IC and TSV technologies
- Pregnancy and preeclampsia studies
- Preterm Birth and Chorioamnionitis
- Maternal and Perinatal Health Interventions
- Low-power high-performance VLSI design
- Optical Network Technologies
- Assisted Reproductive Technology and Twin Pregnancy
- Cancer Risks and Factors
- Electronic Packaging and Soldering Technologies
- Prenatal Screening and Diagnostics
- Renal and related cancers
- Lung Cancer Treatments and Mutations
- Ectopic Pregnancy Diagnosis and Management
- Birth, Development, and Health
- Electrostatic Discharge in Electronics
- Advanced Memory and Neural Computing
- Gestational Diabetes Research and Management
Seoul National University
2005-2020
St. Paul's Hospital
2019
Seoul National University Bundang Hospital
2013-2014
Taiwan Semiconductor Manufacturing Company (United States)
2012
Korean Association Of Science and Technology Studies
2005
Korea Institute of Science and Technology
2005
This paper presents a forwarded-clock receiver (RX) that consists of weight-adjusting sign-sign Mueller-Müller clock and data recovery (CDR) an adaptive decision-feedback equalizer (DFE) with single shared error sampler. Only two samples per bit are utilized for both CDR DFE, which minimizes clocking power consumption. In addition, maximum-eye tracking algorithm is proposed to enhance the vertical eye margin without any extra high-speed analog circuitry. The RX fabricated in 28nm CMOS...
Continuous-rate referenceless clock and data recovery (CDR) circuits are capable of operating over a wide range rates in multiple standards. To achieve wide-range operation without an external reference clock, several frequency detection techniques presented [1]-[5]. However, most the previous require considerable hardware power overhead to obtain information for detection. It leads performance tradeoff between capture range, lock time, consumption. As well as aspects, they rarely address...
A clock generator using an injection-locked oscillator (ILO) offers remarkable jitter performance with low-overhead of additional circuits such as injection switches. Because the cleans edge in every period, accumulation is avoided. However, ILO alone causes a severe reference spur owing to mismatch between desired oscillation frequency set by injected and free-running that could change over process, supply voltage, temperature (PVT) variations. For this reason, continuously tuning...
A 2.5-5.6 GHz low-phase-noise subharmonically injection-locked sub-sampling all-digital phase-locked loop with a dual-edge complementary switched injection technique is presented. While previously reported loops (ILPLLs) require additional circuitry for resolving phase alignment mismatch between the PLL and path, presented ILPLL exhibits simplified architecture owing to proposed bang-bang detector (SSBBPD). Because exploits injection, we analyze performance impact of when inaccurate timing...
To meet the demand for high memory bandwidth, high-bandwidth (HBM) uses a silicon interposer technology to increase number of I/O pins. Interfaces with provide higher throughput (Gb/s/μm) than other packaging technologies due channel density. further, either per-pin data rate or density should be increased. Since increasing requires complex and power-hungry circuitry, is an effective way achieve throughput. However, main problem reducing pitch crosstalk (XT) between adjacent lanes [1]. If...
This article presents design techniques for a continuous-rate reference-free clock and data recovery (CDR) circuit employing stochastic frequency–phase detector (SFPD). By taking histogram-based methodology, optimal weights both frequency phase detection are obtained by utilizing the same information as Alexander detector. The methodology is inductive stochastic, distinguished from conventional, deductive, procedural methods. To verify robust operation, effects of varied patterns, noise,...
In this paper, a low-phase-noise subharmonically injection-locked all-digital phase-locked loop (PLL) with simplified overall architecture based on complementary switched injection technique and sub-sampling bang-bang detector (SSBBPD) is presented. The proposed PLL does not require timing calibration circuit for phase alignment between the loops. Moreover, instead of pulse generator, used to achieve high frequency (e.g. 5 GHz) oscillator. was implemented in 65-nm CMOS process an active area...
This paper presents the reference spur reduction techniques for an analog phase-locked loop (PLL). A simple leakage compensation is proposed, which cancels current of PLL filter with a negligible power overhead. senses from up and down pulse widths in steady state compensates charge loss due to current. systematic approach also proposed. Since operates as band pass frequency domain, can be filtered out by cascading PLLs. The optimization technique cascaded PLLs presented that minimizes...
To achieve ultra small form factor package solution, an ultra-thin (50μm) Si interposer utilizing through-silicon-via (TSV) technology has been developed. Challenges associated with handling thin wafer and maintaining co-planarity have overcome to stack dies (200 μm) on interposer. Improved electrical performance the advantages of this innovative are highlighted in paper. Warpage behavior is investigated simulation experiments ensure reliability robustness stack. Reduction thickness realized...
A 266–2133 MHz phase shifter is proposed for LPDDR4X interface, utilising an all‐digital delay‐locked loop (DLL) and a triangular‐modulated interpolator (PI) to improve the jitter linearity. The DLL consists of two kinds DLLs: global assist fast locking; local which uses adaptive‐window detector folded delay line reduce PI clock waveform achieve good linearity over wide frequency range. prototype chip implemented in 65 nm CMOS process. measured 3.08 ps rms /19.93 pp at 2133 MHz. differential...
An injection-locked phase-locked loop (ILPLL) which continuously tracks the injection timing to achieve improved jitter performance is presented. When not precisely matched with edges of oscillator clock, ILPLL such as and reference spur degrades significantly. To find an optimum timing, a calibration technique proposed that monitors error information from bang-bang phase frequency detector when clock intentionally omitted every other cycle. The calibrator enables robust operation over...
Although an injection-locked oscillator (ILO) can offer excellent jitter performance on average, its intense phase modification at a given injection rate inevitably degrades spur performance, unless timing is carefully controlled. This work investigates behavioral model of the ILO with digital control bang-bang detector (BBPD) discrete-time domain, quantitative analysis dynamics clock multiplier (ILCM) provided. Adjusting frequency error between free-running and signal crucial to obtain...
We examined the psychophysiological effects of navigation in a virtual reality (VR). Subjects were exposed to VR, and required detect specific objects. Ten electrophysiological signals recorded before, during, after VR. Six questionnaires on VR experience acquired from 45 healthy subjects. There significant changes between period pre-VR control several measurements. During period, eye blink, skin conductance level, alpha frequency EEG decreased but gamma wave was increased. Physiological...
As data transfer rates increase, clock frequencies used for high-speed paths also increase. Thus, multiphase clocks are typically utilized in DRAMs to relax timing margins because of the reduced budget. However, phase errors between clocks, due device mismatch, degrade valid sampling window. To reduce error, several correction schemes have been proposed [1]-[4]. The active poly-phase filter-based open-loop scheme exhibits a small RMS jitter contribution, but remaining error after is...
This brief presents an injection-locked PLL (ILPLL) that offers better jitter performance for high-speed clock generation. By analyzing and adjusting a phase domain response (PDR) of the oscillator (ILO), injection strength at target frequency 15 GHz is maximized with lowest deterministic noise. In addition, pulse generator limits maximum operating speed in conventional ILPLL removed to achieve highest synthesizable frequency. Fabricated 28-nm CMOS technology, proposed occupies active area...
In this article, a maximum-eye-tracking clock and data recovery (MET-CDR) circuits for minimum bit error rate (BER) are presented. The proposed CDR does not require BER counter or an eye-opening monitor with any iterative procedure to find the optimal sampling phase. biased level obtained from weighted sum of sampler outputs provides actual eye height (EH) information in presence precursor intersymbol interference (ISI). Two samplers operating on two slightly different timings detect current...
To cope with the rapidly growing data demand, DRAM interface bandwidth also increases steeply each year; for graphics applications, per pin has increased to 27Gb/s/pin, thanks T-coils implemented using RDL layers [1]. As I/O hardware expands, its area and power consumption are increasing. alleviate burden two key ideas proposed in this paper: (1) a PN-over-NP driver capable of impedance matching, without use resistor, significantly reduces chip area, and; (2) T-coil-based edge-boosting...
VR (Virtual Reality) systems have been widely used for various purposes. However, during people's immersion in a virtual environment it is commonly reported that simulation sickness can occur, and prevents us from utilizing wider We constructed controlled analyzing the change of bio-signals immersion, where subjects were requested to find trash cans within five minutes. Each subject's bio-signals, which EEGs 5 different locations, vertical EOG, lead I ECG, fingertip skin temperature,...
A 10-Gb/s, 0.03-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , 1.28-pJ/bit half-rate alldigital injection-locked clock and data recovery (ILCDR) with a path mismatch tracking (PMT) loop is presented. When injection timing not perfectly aligned the phase of oscillator, margin sampler reduced, resulting in degradation jitter tolerance (JTOL) performance. The proposed ILCDR achieves robust behavior over variations by correlating error...
This brief presents a 2.5 - 28 Gb/s multi-standard transmitter with two-step time-multiplexing driver. The proposed driver not only lowers the output parasitic capacitances but also mitigates charge injection by reducing number of stacks compared 4-to-1 In addition, can enhance bandwidth avoiding use 1-unit-interval (1-UI) pulse which is one main design challenges in high-speed transmitters. It provides controllable swing and 3-tap feed-forward equalization (FFE) turning-on -off slices....
This paper presents a data (DQ) receiver for HBM3 with self-tracking loop that tracks phase skew between DQ and strobe (DQS) due to voltage or thermal drift. The selftracking achieves low power small area by utilizing an analog-assisted baud-rate detector. proposed pulse-to-charge (PC) detector (PD) converts the difference detects from difference. An offset calibration scheme can compensates mismatch of PD is also proposed. operates without any additional sensing circuits taking advantage...
This paper presents a 375-GB/s/mm power-efficient memory interface that consists of the PAM-4 transceivers with per-pin training system for next-generation HBM controllers. The self-training executes foreground driver calibration, 2-D sampling point optimization, FFE coefficient adaptation, and sampler offset calibration. Using DC-levels SBR patterns, entire sequence 8 DQ 2 DQS takes less than 1-ms. In addition, charge-recycling saves 44.5% power consumption compared to strongARM latch is...
This brief presents a clocked pluggable optics suitable for high-density data center interconnections. The proposed architecture performs SERDES function at the module side by exploiting forwarded clock from ASIC. Due to relaxed channel loss of ASIC-to-module interface, use power-hungry equalizers can be avoided. Based on an 850-nm multi-mode fiber 25-Gb/s link operation is demonstrated. A vertical-cavity surface-emitting laser-based transmitter outputs optical modulation power 0.6 mW....
This article presents an energy-efficient voltage-mode transmitter with unsegmented output driver that equalizes channel loss in the time domain based on phase delay analysis. By modulating of transmitting clock rather than serialized data stream, proposed significantly reduces data-dependent jitter. The horizontal eye opening is improved by compensating for zero-crossing variation dependent run length transmitted data. scheme complexity eliminating many slices consume large signaling and...