A5023721148- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- VLSI and Analog Circuit Testing
- Electromagnetic Compatibility and Noise Suppression
- Photonic and Optical Devices
- Semiconductor materials and devices
- Semiconductor Lasers and Optical Devices
- Advanced Memory and Neural Computing
- Analog and Mixed-Signal Circuit Design
- Optical Network Technologies
Samsung (South Korea)
2024
Seoul National University
2020-2023
The data-rate requirement for a data center interconnect is being switched to 400 Gb/s. For the optical interface, electro-optical transmitter chip designed in CMOS process has been proposed rather than BiCMOS as technology advances. On other hand, vertical-cavity surface-emitting laser (VCSEL) popular candidate modulation device of GbE because its cost and packaging efficiency [1] –[7]. However, high operating voltage, nonlinear effects, low bandwidth are problems be overcome by VCSEL...
This paper presents a 375-GB/s/mm power-efficient memory interface that consists of the PAM-4 transceivers with per-pin training system for next-generation HBM controllers. The self-training executes foreground driver calibration, 2-D sampling point optimization, FFE coefficient adaptation, and sampler offset calibration. Using DC-levels SBR patterns, entire sequence 8 DQ 2 DQS takes less than 1-ms. In addition, charge-recycling saves 44.5% power consumption compared to strongARM latch is...
This paper presents a 50-Gb/s receiver (RX) with an adaptive phase-shifting (APS) phase detector (PD) for four-level pulse amplitude modulation (PAM-4) clock and data recovery (CDR). The APS PD adopts <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $</tex-math> </inline-formula> to achieve unique locking point that resolves the dead-zone problem caused by combination of conventional baud-rate...
This brief presents a quadrature resonant clock generator for driving four 4.3-mm load wires with tuning capacitors and an amplitude control feedback loop. By using frequency capacitors, which reduce the mismatch in operation LC frequencies, proposed offers power reduction by 20-25% compared conventional CMOS driver 23-34% CML over wide voltage swing. The loop, determines bias current of negative gm cell, maintains constant optimized swing PVT variations. Measurement result from prototype...
This brief presents an 8-GHz Octa-phase Error Corrector (OEC) employing a digital delay-locked loop (DLL) with coprime phase comparison scheme. To alleviate timing constraint during the comparison, clock phases spaced in to 8 is utilized, enabling up 64-Gb/s link operation. In particular, this applies 3T/8 rather than T/8. addition, by clock-divided 5-bit selection scheme, high-speed 8:2 multiplexer (MUX) operates seamlessly without glitches. minimize mismatch and calibration -induced...
This paper proposes a 112 Gb/ s quarter-rate four-level pulse-amplitude modulation (PAM-4) transmitter (TX) using lUI pulse generation based 8:1 multiplexer (MUX) which is adequate for high-speed operation. The includes current-mode logic (CML) driver, quadrature clock generator and phase interpolator (PI) tap 3-tap feed-forward equalizer (FFE). key feature of MUX combining MSB/LSB path with 4:1 serializing to reduce the area power consumption. chip implemented in 28-nm CMOS technology core...
This paper presents a 10-to-12-GHz dual loop quadrature clock corrector consisting of phase error (QEC) and duty-cycle (DCC) using digital delay-locked (DLL). To ensure stability, QEC DCC loops operate concurrently with different bandwidths. The correctors use shared comparator scheme to minimize the calibration-induced error. chip is implemented in 28-nm CMOS technology an active area 0.016 mm2. calibration consume 16.5 mW at 12 GHz on 1.0- V supply, 0.6 ps residual inaccuracy 0.7 % duty cycle
This paper presents an 8-GHz octa-phase clock corrector employing a shared selector-based digital delay-locked loop (DLL). The performs two functions: Octa-phase Error Corrector (OEC) and Duty-Cycle (DCC). phase error is detected via the 3T/8 delay line duty-cycle by utilizing opposing polarity edges in differential without use of additional line. An Edge Converter (EC) designed to match edge propagation through 8:1 MUX EC achieve high level accuracy calibration. Furthermore, save power...