A5074033770- Advancements in PLL and VCO Technologies
- Photonic and Optical Devices
- Optical Network Technologies
- Semiconductor materials and devices
- Semiconductor Lasers and Optical Devices
- VLSI and Analog Circuit Testing
- Radio Frequency Integrated Circuit Design
- Analog and Mixed-Signal Circuit Design
- Thin-Film Transistor Technologies
- Hydraulic and Pneumatic Systems
- CCD and CMOS Imaging Sensors
- Dynamics and Control of Mechanical Systems
- Geophysics and Sensor Technology
- Advanced DC-DC Converters
- Advanced Battery Technologies Research
- Transportation Safety and Impact Analysis
- Silicon and Solar Cell Technologies
- Interconnection Networks and Systems
- Innovative Energy Harvesting Technologies
- Transition Metal Oxide Nanomaterials
Samsung (South Korea)
2004-2025
Seoul National University
2016-2022
This paper presents an ac-dc LED driver that consists of two-parallel inverted buck converters. To buffer the twice-line-frequency energy, one converter (also known as a floating converter) conveys energy to storage capacitor, simultaneously performing power factor correction. The other regulates current maintain constant brightness in LEDs for reducing light flicker low-risk levels. proposed architecture reduces voltage stress and size enabling use film capacitor instead electrolytic...
This paper presents a forwarded-clock receiver (RX) that consists of weight-adjusting sign-sign Mueller-Müller clock and data recovery (CDR) an adaptive decision-feedback equalizer (DFE) with single shared error sampler. Only two samples per bit are utilized for both CDR DFE, which minimizes clocking power consumption. In addition, maximum-eye tracking algorithm is proposed to enhance the vertical eye margin without any extra high-speed analog circuitry. The RX fabricated in 28nm CMOS...
GDDR memory has consistently maintained a leading position in delivering high performance: necessary for applications such as artificial intelligence, deep learning, and data centers. However, achieving an elevated I/O bandwidth, beyond the latest 27Gb/s GDDR6 [1], presents significant challenges ensuring sufficient link budget. One solution is using multi-level pulse amplitude modulation (PAM) signaling. In GDDR7 specification, single-ended PAM3 signaling used to achieve higher rates it can...
We presents an energy-efficient PAM-4 transmitter that provides a controlled output impedance, scalable voltage swing, and fractionally spaced feed-forward equalization (FFE). By using resistive-feedback driver, the proposed can reduce power dissipation in pre-driver stages compared with conventional transmitters. It also offers more straightforward implementation of 3-tap FFE owing to simple current-summing structure pre-driver. In addition, impedance driver is by regulating Gm cell, which...
This brief presents a programmable phase detector (PD) for the Baud-rate clock and data recovery (CDR) in four-level pulse amplitude modulation (PAM-4) quarter-rate receiver, using transition weighted gain (TWG) technique. By assigning different to detection each data-level transition, TWG-based CDR (TWG-CDR) achieves stable operation of jitter tracking. An optimal transfer characteristic is obtained by highest weight on 1-level lowest 3-level transition. The proposed fabricated 40 nm CMOS...
In order to suppress the malfunction caused by shift of threshold voltage (VTH) oxide thin film transistors (TFTs) a negative value, double-gate TFTs are used in register gate driving system control VTH adjusting top bias. The proposed circuit detects current consumption and adjusts so that is regulated within desired value. includes compensation algorithm, which can search for an optimized bias various circumstances such as process fluctuations ambient temperature change. provides stable...
This brief presents a 2.5 – 32 Gb/s Gen 5-PCIe receiver with multi-rate clock and data recovery (CDR) engine hybrid decision feedback equalizer (DFE). The for the PCIe requires wide-range operation compensation high insertion loss. proposed CDR enables to operate clocking schemes according rates, which does not need any additional high-speed analog circuits normally used operation. In addition, DFE architecture only meets timing constraint but also reduces equalization power. By using...
This brief presents a 2.5 - 28 Gb/s multi-standard transmitter with two-step time-multiplexing driver. The proposed driver not only lowers the output parasitic capacitances but also mitigates charge injection by reducing number of stacks compared 4-to-1 In addition, can enhance bandwidth avoiding use 1-unit-interval (1-UI) pulse which is one main design challenges in high-speed transmitters. It provides controllable swing and 3-tap feed-forward equalization (FFE) turning-on -off slices....
The shift register of display panel employing double‐gate oxide thin‐film transistors (TFTs) to compensate the severe degradation threshold voltage ( V TH ) is proposed. In TFTs, controlled by adjusting top‐gate bias, so that can be stabilised bias control. However, an optimum varies from product due process–voltage–temperature variation. To overcome this variation, a feedback system designed and fabricated in 0.18 μm BCDMOS process. consists current sensing searching algorithm for finding...
A 10 Gb/s PAM-4 transmitter (TX) with a modulo-based equalization technique is presented. The proposed feed-forward Tomlinson-Harashima precoding (FF-THP) scheme takes advantage of both (THP) and (FFE). vertical eye margin (VEM) enhanced by removing the precursor inter-symbol interference (ISI) pretaps while incorporating modulo operation. VEMs methods are derived based on z-domain response (ZDR). effectiveness FF-THP examined quantitative analysis numerical simulation. Especially for...
This paper presents a 2x-oversampling clock-and-data recovery (CDR) scheme with golden section search (GSS) algorithm [1] of 32 Gb/s non-return-to-zero (NRZ) receiver. The proposed CDR GSS adaptively selects the optimum sampling phase data clock as well recovering edge clock. It operates fast without requiring slow procedures such BER measurement. To control phases and clock, two parallel interpolators (PI) are used. After locks, difference between is adjusted by algorithm. Assuming an eye...
This paper presents a low-power implementation of 64 Gb/s PAM-4 transmitter (TX) by using 3-tap feed-forward equalization (FFE) and G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -regulated active-feedback driver. The FFE tap generation is merged into serializer to minimize the overhead FFE, replacing power-hungry delay generator. An inverter based driver also proposed achieve larger output swing compared with resistive- feedback...
A semi-actively controlled impact systemis studied, which adjusts an impulse exerted by the external impact. Also, active control system using a servo valve is introduced, and these performances are compared. The systems should respond to extremely short within highly fast interval. Both semi-active utilize orifice in form of proportional or valve, its opening area pressure piston displacement. These devices overcome temperature viscosity variations due continuant operations, keep desired...
This paper presents a 36 GS/s data path that is based on CMOS logic. The proposed non-clocked delay generator achieves high bandwidth as well produces near-1-UI by employing digitally controlled cross-coupled latches. In addition, the 4-to-2 serializer with pre-charging/discharging transistors not only reduces data-dependent jitter but also mitigates non-ideal effects such charge injection and clock feedthrough removing floating nodes of multiplexer. As result, 8-to-2 has extremely low rms...