A5101945638- Semiconductor materials and devices
- Advanced Memory and Neural Computing
- Thin-Film Transistor Technologies
- CCD and CMOS Imaging Sensors
- Ferroelectric and Negative Capacitance Devices
- Advancements in Semiconductor Devices and Circuit Design
- Solid-state spectroscopy and crystallography
- Crystal Structures and Properties
- Advanced Materials Characterization Techniques
- Electronic and Structural Properties of Oxides
- Rare-earth and actinide compounds
- Semiconductor materials and interfaces
- Inorganic Chemistry and Materials
- Transition Metal Oxide Nanomaterials
- Advanced Battery Technologies Research
- Crystallography and Radiation Phenomena
- Analog and Mixed-Signal Circuit Design
- Radiation Effects in Electronics
- Topological Materials and Phenomena
- Advancements in Battery Materials
- Electron and X-Ray Spectroscopy Techniques
- Nonlinear Optical Materials Research
- Low-power high-performance VLSI design
- Phase-change materials and chalcogenides
Semiconductor Energy Laboratory (Japan)
2011-2019
Osaka Prefecture University
2008-2011
Emerging nonvolatile memory with an oxide–semiconductor-based thin-film transistor (TFT) using indium-gallium-zinc-oxide (IGZO) was developed. The is called oxide–semiconductor random access (NOSRAM). cell of the NOSRAM (NOSRAM cell) consists IGZO TFT for data writing, a normal Si-based p-channel metal-oxide-semiconductor (PMOS) reading, and capacitor storing charge controlling PMOS gate voltage. are formed over PMOS. Owing to extremely low-leakage-current characteristics TFT, stored in 2-fF...
We propose Non-Volatile Oxide Semiconductor Random Access Memory (NOSRAM) that is a novel memory including transistor using an oxide semiconductor, In-Ga-Zn Oxide. OS transistors feature extremely low leakage current of about 100-600 yA/μm (1 yA = 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-24</sup> A) at 85°C for example, and are applicable to elements. Our prototype 1Mb NOSRAM has achieved...
A 3bit/cell nonvolatile oxide semiconductor RAM (NOSRAM) test die comprising c-axis aligned crystal In-Ga-Zn-O TFTs has been fabricated. The write time of the is 100 ns. collectively reads multilevel data within 900 ns with a 3bit A/D converter serving as reading circuit. endurance NOSRAM cell more than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cycles.
An embedded 1 Mbit 2T1C gain-cell memory macro using indium-gallium-zinc oxide semiconductor FETs (OSFETs) with an extremely low off-state current of less than zA (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-21</sup> A) was fabricated. In the gain cell, OSFET for write operation stacked over a SiFET read operation. The fabricated combination 60-nm and 65-nm CMOS processes. It achieves 140 MHz data retention more h. Its static power in...
Using data retention circuits that include crystalline oxide semiconductor transistors as backup for power gating, a processor system can reduce standby leakage current significantly. This is effective in the Internet of Things (IoT) applications require reduction. The transistor constitute nonvolatile circuit easily because it exhibits significantly lower off-state than silicon and highly compatible with CMOS logic circuit. achieve 2-clock-cycle 4-clock-cycle restore; thus, efficiently...
A flip-flop achieving high-speed backup utilizing a Si transistor and long-term retention with zero standby power by means of c-axis aligned crystalline (CAAC) In-Ga-Zn oxide, kind CAAC oxide semiconductor, featuring extremely low off-state current is proposed. Using the flip-flop, 32-bit processor has been fabricated 350-nm Si/180-nm semiconductor technology, demonstrated data shutdown in 1.5 clock cycles at 1.77 nJ, recovery 2.5 cycles, for least day. According to simulation results, fast...
The progress in emerging memory featuring indium–gallium–zinc oxide semiconductor field-effect transistors (OSFETs) is overviewed. An OSFET exhibits an extremely low off-state current the order of zeptoamperes (zA or 10-21 A). process embedded into a conventional CMOS process, and stacked over SiFET. OSFET-based achieves high speed, voltage writing endurance. Using enables low-power ULSI such as with very refresh rate processor without any leakage power. Oxide key device that ULSI, it can...
We have studied the electronic structure of EuPd2Si2 by hard X-ray photoelectron spectroscopy (HX-PES) from 300 to 20 K. The temperature-dependent HX-PES spectra clearly show valence transition, namely, intensities divalent and trivalent Eu 3d components are abruptly changed. change in spectral shape, especially drastic feature with temperature, can be explained within framework Anderson model. peak shift Pd core level temperature indicates that electrons contribute temperature-induced...
Development of LSI targeting artificial intelligence (AI) has accelerated, some chips have been used and are commercially available in a number applications. capable performing arithmetic operation for deep learning, etc., at low power high speed is crucial achieving more sophisticated AI. Power consumption increasing significantly owing particularly to the practical use AI, reduction techniques urgently necessary.
We have prototyped a microcontroller (MCU) that employs crystalline In-Ga-Zn oxide transistors having an extremely low off current below 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-21</sup> A. The IGZO-based MCU can retain data during power gating in both of its processing unit and memory, there is integrated voltage regulator store the reference voltage. with combination 60-nm IGZO (in BEOL) 110-nm Si CMOS processes. It has standby 880...
Abstract The temperature dependence of the core‐level and valence‐band electronic structures TlGaTe 2 TlInSe that exhibits high values Seebeck coefficient has been studied by hard X‐ray photoemission spectroscopy over range 40–450 K. relative peak position width for Tl 4f, Ga 2p Te 3d in are determined. It is shown not only chemical shift defying but also electron‐phonon interaction responsible line‐broadening rather peculiar behaviour reflects incommensurate phase transition. Thermoelectric...
As the number of devices connected to Internet increases, servers and mobile must process increasingly large volumes data, also accommodate increasing demand for high-speed large-capacity working memory keeping power consumption low. This need is being fulfilled by emerging devices, such as resistive RAM, phase-change MRAM [1], which realize high-speed, high-density nonvolatile memory, significantly enhancing performance CPUs with integrated memories.
Li-ion batteries are primarily used as power sources in electronic devices and electric vehicles offer substantial conveniences to consumers. However, fires have broken out likely due micro short-circuit (also called internal or soft shortcircuit) [1]. The is a failure mode where Li metal first precipitates on negative electrode then reaches positive electrode; eventually occurs between the electrodes battery voltage slightly decreases. Repetitive occurrences of will generate heat lead...
This letter presents a microcontroller unit (MCU) that employs <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</i> -axis aligned crystalline indium-gallium-zinc oxide semiconductor FET (CAAC-IGZO FET) with an extremely low off-state current below the zepto-ampere (10 <sup xmlns:xlink="http://www.w3.org/1999/xlink">-21</sup> A) level. MCU based on IGZO-FETs has logic circuits and memory macros can retain data even when power supply is turned off,...
A chip of embedded SRAM having backup circuits using a 60-nm c-axis aligned crystalline oxide semiconductor (CAAC-OS) such as CAAC indium-gallium-zinc (CAAC-IGZO) and Cortex-M0 core flip-flops with CAAC-OS is fabricated. The M0 can retain data the during power-off; thus, they perform power gating (PG) time 100 ns recovery 10 clock cycles (including restoration (100 ns)). Further, memory cell area performance in combining 45-nm Si are estimated to have negligible overhead.
We have studied the electronic structure of EuPd 2 Si by hard X-ray photoelectron spectroscopy (HX-PES) from 300 to 20 K. The temperature-dependent HX-PES spectra clearly show valence transition, namely, intensities divalent and trivalent Eu 3d components are abruptly changed. change in spectral shape, especially drastic feature with temperature, can be explained within framework Anderson model. peak shift Pd core level temperature indicates that electrons contribute temperature-induced transition .
SRAM with backup circuits using a crystalline oxide semiconductor (OS) (e.g., c-axis aligned (CAAC-OS) typified by CAAC In-Ga-Zn (CAAC-IGZO)) is reported. Results of cell-level simulation based on 45-nm Si/100-nm OS process technology show time 3.9 ns, recovery 2.0 and break-even 21.7 ns. The OS-SRAM cell can replace standard-SRAM without area overhead, which does not significantly affect normal operation. A 32-bit microprocessor test chip (350-nm Si/180-nm technology) cache memory including...
As leakage power continues to increase when transistor sizes are downscaled, it becomes increasingly hard achieve low consumption in modern chips. Normally-off processors use state-retention and non-volatile circuits make gating more efficient with less static power. In this paper, we propose two novel flip-flop designs based on a parallel series retention circuit architectures utilizing crystalline indium gallium zinc oxide transistors, which can state zero To demonstrate the application of...
A 16-level cell is demonstrated using a test chip of nonvolatile oxide semiconductor RAM comprising c-axis aligned crystalline In-Ga-Zn FETs. read circuit composed voltage followers outputs with maximum distribution 37 mV. single follower has the 25.3 200 ns write time demonstrated.
Abstract We demonstrate a 16-level cell using nonvolatile oxide semiconductor random access memory test chip based on c -axis-aligned – b -plane-anchored crystal In–Ga–Zn (CAAC-IGZO) FETs. The consists of CAAC-IGZO FET, p-channel metal–oxide–semiconductor Si and capacitor. Data are written threshold voltage cancel write method, read circuit composed followers outputs voltage. Using 200 ns time the chip, obtained maximum distribution width is 37 mV in case 32768 cells. distributions 16...
Using data retention circuits that include crystalline oxide semiconductor transistors as backup for power gating, a processor system can reduce standby leakage current significantly. This is effective in the Internet of Things (IoT) applications require reduction. The transistor constitute nonvolatile circuit easily because it exhibits significantly lower off-state than silicon and highly compatible with CMOS logic circuit. achieve 2-clock-cycle 4-clock-cycle restore; thus, efficiently...
2013 International Conference on Solid State Devices and Materials,Zero Area Overhead Retention Flip Flop Utilizing Crystalline In-Ga-Zn Oxide Thin Film Transistor with Simple Power Control Implemented in a 32-bit CPU
Electronic energy bands of the Tl-based ternary chalcogenide TlGaTe2 with a quasi one-dimensional crystalline structure have been studied by means high resolution angle-resolved photoemission spectroscopy (ARPES) in order to check for dispersive structures similar Dirac cone observed surface Bi-based binary chalcogenides. Two linear which are not reproduced band calculations bulk material along Γ–N direction perpendicular chains. These dispersions form cross-type that is centered at Γ point...