- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Semiconductor materials and devices
- Magnetic properties of thin films
- Radiation Effects in Electronics
- VLSI and Analog Circuit Testing
- Low-power high-performance VLSI design
- Parallel Computing and Optimization Techniques
- Experimental Learning in Engineering
- Advancements in Semiconductor Devices and Circuit Design
- Embedded Systems Design Techniques
- Evolutionary Algorithms and Applications
- Interconnection Networks and Systems
- Advanced Data Storage Technologies
- VLSI and FPGA Design Techniques
- Engineering Education and Curriculum Development
- Quantum-Dot Cellular Automata
- Neural Networks and Applications
- Physical Unclonable Functions (PUFs) and Hardware Security
- Advanced Neural Network Applications
- Sparse and Compressive Sensing Techniques
- Quantum and electron transport phenomena
- CCD and CMOS Imaging Sensors
- Distributed systems and fault tolerance
- Neural Networks and Reservoir Computing
University of Central Florida
2015-2024
Orlando Health
2014-2024
Institute of Electrical and Electronics Engineers
2020-2022
Canadian Standards Association
2020-2022
Artistic Realization Technologies
2020-2021
Spectrum Research (United States)
2019-2020
University of Hartford
2020
Sharif University of Technology
2020
University of South Carolina
2020
Seoul National University
2020
Quantum-dot cellular automata (QCA) has been studied extensively as a promising switching technology at nanoscale level. Despite several potential advantages of QCA-based designs over conventional CMOS logic, some deposition defects are probable to occur in systems which have necessitated fault-tolerant structures. Whereas binary adders among the most frequently-used components digital systems, this work targets designing highly-optimized robust full adder QCA framework. Results demonstrate...
Resiliency of exascale systems has quickly become an important concern for the scientific community. Despite its importance, still much remains to be determined regarding how faults disseminate or at what rate do they impact HPC applications. The understanding where and fast propagate could lead more efficient implementation application-driven error detection recovery.
A novel Parity-Preserving Reversible Gate (PPRG) is developed using Quantum-dot Cellular Automata (QCA) technology. PPRG enables rich fault-tolerance features, as well reversibility attributes sought for energy-neutral computation. Performance of the design validated through implementing thirteen standard combinational Boolean functions three variables, which demonstrate from 10.7 to 41.9 percent improvement over previous gate counts obtained with other reversible and/or preserving designs....
Magnetic tunnel junction (MTJ)-based devices have been studied extensively as a promising candidate to implement hybrid energy-efficient computing circuits due their nonvolatility, high integration density, and CMOS compatibility. In this paper, MTJs are leveraged develop novel full adder (FA) based on 3- 5-input majority gates. Spin Hall effect (SHE) is utilized for changing the MTJ states resulting in low-energy switching behavior. SHE-MTJ modeled Verilog-A using precise physical...
In this paper, we leverage magnetic tunnel junction (MTJ) devices to design an energy-efficient nonvolatile lookup table (LUT), which utilizes a spin Hall effect (SHE) assisted switching approach for MTJ storage cells. SHE-MTJ characteristics are modeled in Verilog-A based on precise physical equations. Functionality of the proposed SHE-MTJ-based LUT is validated using SPICE simulation. Our (SHE-LUT) compared with most MTJ-based circuits. The obtained results show more than 6%, 37%, and 67%...
Spin-transfer torque (STT) random access memory has been researched as a promising alternative for static in reconfigurable fabrics, particularly lookup tables (LUTs), due to its nonvolatility, low standby and power, high integration density features. In this brief, we leverage physical characteristics of magnetic tunnel junctions (MTJs) design unique reference MTJ which calibrated resistance matching the STT-based LUT (STT-LUT) circuit requirements provide optimal reading operation. Results...
Magnetoresistive random access memory (MRAM) technologies with thermally unstable nanomagnets are leveraged to develop an intrinsic stochastic neuron as a building block for restricted Boltzmann machines (RBMs) form deep belief networks (DBNs). The embedded MRAM-based is modeled using precise physics equations. simulation results exhibit the desired sigmoidal relation between input voltages and probability of output state. A probabilistic inference network simulator (PIN-Sim) developed...
Promising for digital signal processing applications, approximate computing has been extensively considered to tradeoff limited accuracy improvements in other circuit metrics such as area, power, and performance. In this paper, arithmetic circuits are proposed by using emerging nanoscale spintronic devices. Leveraging the intrinsic current-mode thresholding operation of devices, we initially present a hybrid spin-CMOS majority gate design based on composite device structure consisting...
For the sake of higher cell density while achieving near-zero standby power, recent research progress in Magnetic Tunneling Junction (MTJ) devices has leveraged Multi-Level Cell (MLC) configurations Spin-Transfer Torque Random Access Memory (STT-RAM). However, orderto mitigate write disturbance an MLC strategy, data stored soft bit must be restored back immediately after hard switching is completed. Furthermore, as result MTJ feature size scaling, can expected to become disturbed by read...
Domain wall nanomagnet (DWNM)-based devices have been extensively studied as a promising alternative to the conventional CMOS technology in both memory and logic implementations due their non-volatility, near-zero standby power, high integration density characteristics. In this paper, we leverage physics-based model of DWNM device design highly scalable current-mode majority gate achieve novel one bit full-adder (FA) circuit. The modeled specifications are calibrated with experimentally...
A low-energy hardware implementation of deep belief network (DBN) architecture is developed using near-zero energy barrier probabilistic spin logic devices (p-bits), which are modeled to realize an intrinsic sigmoidal activation function. CMOS/spin based weighted array structure designed implement a restricted Boltzmann machine (RBM). Device-level simulations on precise physics relations used validate the relation between output probability p-bit and its input currents. Characteristics...
In this article, we propose field programmable gate array-based scalable architecture for discrete cosine transform (DCT) computation using dynamic partial reconfiguration. Our can achieve quality scalability This is important some critical applications that need continuous hardware servicing. has three features. First, the perform DCT computations eight different zones, is, from 1 × to 8× 8 DCT. Second, change configuration of processing elements trade off precisions coefficients with...
Spin-Transfer Torque Random Access Memory (STT-MRAM) has been explored as a post-CMOS technology for embedded and data storage applications seeking non-volatility, near-zero standby energy, high density. Towards attaining these objectives practical implementations, various techniques to mitigate the specific reliability challenges associated with STT-MRAM elements are surveyed, classified, assessed in this article. Cost suitability metrics include area of nanomagmetic CMOS components per...
A Generative Adversarial Network (GAN) is an adversarial learning approach which empowers conventional deep methods by alleviating the demands of massive labeled datasets. However, GAN training can be computationally-intensive limiting its feasibility in resource-limited edge devices. In this paper, we propose approximate (ApGAN) for accelerating GANs from both algorithm and hardware implementation perspectives. First, inspired binary pattern feature extraction method along with binarized...
Analog electronic nonvolatile memories mimicking synaptic operations are being explored for the implementation of neuromorphic computing systems. Compound synapses consisting ensembles stochastic binary elements alternatives to analog memory achieve multilevel operation. Among existing technologies, magnetic tunneling junction (MTJ)-based random access (MRAM) technology has matured point commercialization. More importantly this work, stochasticity is natural MTJ switching physics, e.g.,...
Spin-Transfer Torque Random Access Memory (STT-RAM) has been identified as an advantageous candidate for on-chip memory technology due to its high density and ultra low leakage power. Recent research progress in Magnetic Tunneling Junction (MTJ) devices developed Multi-Level Cell (MLC) STT-RAM further enhance cell density. To avoid the write disturbance MLC strategy, data stored soft bit must be restored back immediately after hard switching is completed. However, frequent restores are not...
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It is widely accepted that the difficulty and expense involved in acquiring knowledge behind tactical behaviors has been one limiting factor development of simulated agents representing adversaries teammates military game simulations. Several researchers have addressed this problem with varying degrees success. The mostly lies fact difficult to elicit represent through interactive sessions between model developer subject matter expert. This paper describes a novel approach employs genetic...
The evaluation of conversational dialog systems has remained a controversial topic, as it is challenging to quantitatively assess how well conversation agent performs, or much better one compared another. Furthermore, the hurdles which remains elusive in this quandary definition naturalness, demonstrated by system can maintain natural flow devoid perceived awkwardness. As step towards defining dimensions effectiveness and naturalness system, paper identifies existing practices are then...
Nanotechnologies, notably Quantum-dot Cellular Automata (QCA), provide an attractive perspective for future computing technologies. In this paper, (QCA) is investigated as implementation method reversible logic. A novel XOR gate and also a new approach to implement 2:1 multiplexer are presented. Moreover, efficient potent universal based on the proposed designed. The has superb performance in implementing QCA standard benchmark combinational functions terms of area, complexity, power...