In a discrete multitone receiver, time-domain equalizer (TEQ) reduces the intersymbol interference (ISI) by shortening effective duration of channel impulse response. Current TEQ design methods such as minimum mean-squared error (MMSE), maximum SNR (MSSNR), and geometric (MGSNR) do not directly maximize bit rate. We develop two to First, we partition an equalized multicarrier into its equivalent signal, noise, ISI paths new subchannel definition. Then, derive nonlinear function taps that...

Ultra wideband (UWB) is a promising technique for wireless communications. It carrier-free (base-band) technique, which can greatly reduce the complexity and cost of transceiver. In contrast with conventional communication systems using "sine wave", UWB information carried in very short pulse, covers an extremely wide spectrum bandwidth. Several candidate monocycle (narrow pulse) shapes are investigated, their characteristics BER performance AWGN pulse position modulation (PPM) simulated,...

We present a new class of blind cyclic-based estimators for carrier frequency-offset and symbol-timing error estimation orthogonal frequency-division multiplexing (OFDM) systems. The proposed approach exploits the properties cyclic prefix subset to reveal synchronization parameters in likelihood function received vector. A joint timing is derived, which globally characterizes problem. resulting probabilistic measure used develop three classes unbiased estimators, namely, maximum-likelihood,...

The design and analysis of a fully integrated multistage interleaved synchronous buck dc-dc converter with on-chip filter inductor capacitor is presented. designed fabricated in 0.18 mum SiGe RF BiCMOS process technology generates 1.5 V-2.0 V programmable output voltage supporting maximum current 200 mA. High switching frequency 45 MHz, multiphase operation, fast hysteretic controller reduce the sizes by two orders magnitude compared to state-of-the-art converters enable converter. does not...

Ring oscillators (ROs) provide a low-cost digital VCO solution in fully integrated PLLs. However, due to their supply noise sensitivity and high floor, applications have been limited low-performance applications. The proposed architecture introduces an analog feed-forward adaptive phase-noise cancellation that extracts suppresses phase of ROs outside the PLL bandwidth. technique can improve at arbitrary offset frequency bandwidth, and, after initial calibration for gain, it is insensitive...

CMOS folded source-coupled logic (FSCL) uses a smaller voltage swing ( Delta V/sub L/ approximately=0.2 dd/) than conventional static and achieves power-delay product at high operating frequencies. By using current-steering techniques in fully-differential FSCL circuits to maintain constant power supply current, digital switching noise is reduced by 30-300 times compared logic. Measured results are presented for gates fabricated 2- mu m process, simulated with standard 1- process used...

This paper presents an output external capacitor-less, fully integrated, fast settling NMOS low-dropout (LDO) regulator with adaptively biased error amplifier (EA) for system-on-chip core applications. The adaptive biasing technique increases both loop bandwidth and slew-rate of the LDO by 100% at full load condition without changing no-load quiescent current. Direct feedback to gate-to-source voltage regulation FET provides transient response. proposed employs a cross-coupled common-gate...

A combined class-AB and switch-mode regulator based supply modulator with a master-slave architecture achieving wide bandwidth low ripple is presented. Low frequency content of the envelope waveform provided by synchronous-rectifier power while high rail-to-rail amplifier. range, loss output current sensing circuit used at amplifier output, canceling due to extending overall bandwidth. The proposed designed fabricated on 0.35 mum CMOS process. achieves maximum efficiency 82% an IMD3 65 dBc...

A combined linear and delta-modulated (DeltaM) switch-mode PA supply modulator for polar transmitters in wireless handsets is designed a 0.25 mum CMOS process. The employs DeltaM DC-DC buck converter to enhance the efficiency of regulator at backed-off voltages powers. delta-modulator's noise-shaping characteristic, regulator's power rejection, digital pre-emphasis input envelope, closed-loop amplitude path from output are simultaneously used achieve state-of-the-art performance. presented...

A low-power transceiver for medical implant communication service is presented. The device consists of three subsystems, which perform wake-up signal reception, data-link binary frequency-shift keying (BFSK) and transmission, respectively. common antenna interface reused in the reducing circuit complexity number external components. Super-regenerative architecture used g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosted...

Wearable devices with sensing, processing and communication capabilities have become feasible the advances in internet-of-things (IoT) low power design technologies. Energy harvesting is extremely important for wearable IoT due to size weight limitations of batteries. One most widely used energy sources photovoltaic cell (PV-cell) owing its simplicity high output power. In particular, flexible PV-cells offer great potential applications. This paper models, first time , how bending a PV-cell...

Digital low-dropout (DLDO) regulators are gaining attention due to their design scalability for distributed multiple voltage domain applications required in state-of-the-art system-on-chips. Due the discrete nature of output current and discrete-time control loop, steady-state response DLDO has inherent ripple. A hybrid (HD-LDO) with fast stable operation across a wide load range while reducing ripple is proposed. In HD-LDO, low analog cancellation amplifier (RCA) work parallel. The dc RCA...

Two integrated polar supply-modulated class E and F power amplifiers (PAs) in 0.18-mum SiGe BiCMOS process are presented. The used to transmit GSM-EDGE signals with an envelope dynamic range of 11 dB a frequency 880-915 MHz. use switch-mode dc-dc buck converters for supply modulation, where sigma-delta (SigmaDeltaM), delta (DeltaM), pulsewidth modulation modulate the PA amplitude signal. A framework has been developed comparing three switching techniques EDGE implementation. measurement...

A noise-shaped direct digital IF to RF (DIF2RF) DAC with embedded upconverter mixer is presented. The signal noise shaped by a bandpass Sigma-Delta modulator 1-bit output followed semidigital finite impulse response (FIR) filter. current mode FIR filter combines scaled values of the local oscillator (LO) for performing reconstruction filtering and upconversion in single module. DIF2RF design modulates LO signal. This topology eliminates transconductance nonlinearity conventional mixers...

A microelectromechanical-systems (MEMS)-based electromagnetically actuated loudspeaker to reduce form factor, cost, and power consumption, increase energy efficiency in hearing-aid applications is presented. The MEMS has multilayer copper coils, an NiFe soft magnet on a thin polyimide diaphragm, NdFeB permanent the perimeter. coil impedance measured at 1.5 Omega, resonant frequency of diaphragm located far from audio range. device driven by power-scalable, 0.25-mum complementary metal-oxide...

A fully integrated output capacitor-less, nMOS regulation FET low-dropout (LDO) regulator with fast transient response for system-on-chip power applications is presented. The error amplifier (EA) consists of a differential cross-coupled common-gate (CG) input stage achieving twice the transconductance and unity-gain-bandwidth in comparison to conventional common-source stage. low resistance CG EA improves stability LDO over wide range load currents. employs currentreused dynamic biasing...

A fully differential source-coupled logic technique intended for mixed-mode applications has been developed. Implemented in 2- mu m CMOS technology with a 5.0-V supply, the minimum propagation delay is about 750 ps an 800-mV swing. Power supply current spikes are reduced by two orders of magnitude compared to conventional static logic.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The application of series-gated, multiplexer-minimization, and variable-entered mapping methods to the synthesis fully differential CMOS folded source-coupled logic (FSCL) gates is described. In contrast conventional static logic, FSCL dissipates DC power. Its total power consumption competitive at higher speeds where its low digital switching noise most advantageous. minimum propagation delay a simple gate compares favorably gate. Complex functions are generally faster in since topology...

An on-chip clock phase-noise measurement circuit is presented. Unlike previously reported monolithic techniques that measure jitter in the time domain, proposed module measures spectrum. The fully integrated and does not require a spectrally clean reference or any external calibration. can be as part of built-in self-test (BIST) scheme for PLL synthesizers. uses low-noise voltage-controlled delay-line (VCDL) mixer-based frequency discriminator to extract fluctuations at baseband. A...

Polar modulation has been proven to be an effective way build high-efficiency high-linearity power amplifier systems. In a polar transmitter, non-linear amplifiers can used for linearly modulated waveforms. Because of envelope bandwidth expansion in transmitters, the design wide-bandwidth supply modulator is one most challenging aspects transmitter. The common technique providing low-noise linear system PA by using low-dropout regulators, however at backed-off levels their efficiencies are...

An adaptive blocker-rejection wideband continuous-time (CT) sigma-delta (SigmaDelta) analog-to-digital converter (ADC) is presented. integrated blocker detector reconfigures the ADC loop architecture to avoid overloading in presence of strong interferers, improving receiver channel selectivity and sensitivity without increasing its dynamic range (DR) requirements. The operation relaxes baseband filtering requirements for a worldwide inter-operability microwave access (WiMAX, IEEE 802.16e)...

Several wireless biomedical transceivers, including medical implants communication systems (MICSs), require ultra-low-power low-complexity frequency synthesizers. This paper presents an all-digital frequency-locked loop (ADFLL)-based synthesizer with a built-in frequency-shift keying modulator for MICS and industrial-scientific-medical band applications. Unlike phase-locked loops that rely on power-hungry time to digital converter, the proposed ADFLL employs high-resolution single-bit ΣΔ...

A wideband hybrid Envelope tracking (ET) modulator utilizing a hysteretic-controlled three-level switching converter (3L-SWC) and slew-rate enhanced linear amplifier (LA) are presented. In addition to smaller ripple lower losses of 3L-SWCs, employing the proposed hysteresis control loop results in higher speed wider bandwidth converter, enabling over 80 MHz frequency. concurrent sensor circuit monitors regulates flying capacitor voltage VCF eliminates conventionally required calibration it....

Frequency synthesizers are fundamental building blocks in radio frequency, communications, and analog signal processing for generating high accuracy oscillatory signals. In general, the frequency synthesizer is most sensitive block system since many of elements such as clock, filters, up/down converters depend on a clean sinusoidal at given frequency. For radiation environments, response sensitivity phase-lock loop (PLL) very critical. This paper examines effect single events (SEE) PLL...

A dual-channel directional digital hearing aid front end using microelectromechanical-systems microphones, and an adaptive-power analog processing signal chain are presented. The consists of a double differential amplifier-based capacitance-to-voltage conversion circuit, 40-dB variable gain amplifier (VGA) power-scalable continuous time sigma delta analog-to-digital converter (ADC), with 68-dB signal-to-noise ratio dissipating 67 μ W from 1.2-V supply. MEMS microphones fabricated standard...