A5036095997- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Neural dynamics and brain function
- Neural Networks and Reservoir Computing
- Neural Networks and Applications
- Advanced SAR Imaging Techniques
- Neuroscience and Neural Engineering
- Digital Transformation in Industry
- Physical Unclonable Functions (PUFs) and Hardware Security
- IoT and Edge/Fog Computing
- Modular Robots and Swarm Intelligence
- Radar Systems and Signal Processing
- Flow Measurement and Analysis
- Anomaly Detection Techniques and Applications
- Radio Frequency Integrated Circuit Design
- Time Series Analysis and Forecasting
- Infrared Target Detection Methodologies
- Low-power high-performance VLSI design
- CCD and CMOS Imaging Sensors
- Digital Filter Design and Implementation
- Numerical Methods and Algorithms
Technische Universität Dresden
2020-2025
This paper introduces the processing element architecture of second generation SpiNNaker chip, implemented in 22nm FDSOI. On circuit level, chip features adaptive body biasing for near-threshold operation, and dynamic voltage-and-frequency scaling driven by spiking activity. system is centered around an ARM M4 core, similar to processor-centric first SpiNNaker. To speed operation subtasks, we have added accelerators numerical operations both (SNN) rate based (deep) neural networks (DNN). PEs...
Abstract We implemented two neural network based benchmark tasks on a prototype chip of the second-generation SpiNNaker (SpiNNaker 2) neuromorphic system: keyword spotting and adaptive robotic control. Keyword is commonly used in smart speakers to listen for wake words, control applications adapt unknown dynamics an online fashion. highlight benefit multiply-accumulate (MAC) array 2 which ordinarily rate-based machine learning networks when employed neuromorphic, spiking context. In...
With the advent of high-density micro-electrodes arrays, developing neural probes satisfying real-time and stringent power-efficiency requirements becomes more challenging. A smart probe is an essential device in future neuroscientific research medical applications. To realize such devices, we present a 22 nm FDSOI SoC with complex on-chip data processing training for signal analysis. It consists digitally-assisted 16-channel analog front-end 1.52 μW/Ch, dedicated bio-processing accelerators...
The joint progress of artificial neural networks (ANNs) and domain specific hardware accelerators such as GPUs TPUs took over many domains machine learning research. This development is accompanied by a rapid growth the required computational demands for larger models more data. Concurrently, emerging properties foundation in-context drive new opportunities applications. However, cost applications limiting factor technology in data centers, importantly mobile devices edge systems. To mediate...
Industrial plants suffer from a high degree of complexity and incompatibility in their communication infrastructure, caused by wild mix proprietary technologies. This prevents transformation towards Industry 4.0 the Internet Things. Open Platform Communications Unified Architecture (OPC UA) is standardized protocol that addresses these problems with uniform semantic across all levels hierarchy. However, its adoption embedded field devices, such as sensors actors, still lacking due to...
Neuromorphic hardware has been emerging in recent years, seeking various applications to explore its uniqueness, limitations, and possibilities. As a representative application research area, gesture recognition is gaining wider popularity, while the conflict of spiking neural network (SNN) size available memory neuromorphic edge-AI can be thorny issue, which even intensified by demand for continuously processing input data stream from sensor real-world scenario since certain amount required...
SpiNNaker is an efficient many-core architecture for the real-time simulation of spiking neural networks. To also speed up deep networks (DNNs), 2nd generation SpiNNaker2 will contain dedicated DNN accelerators in each processing element. When realizing large CNNs on SpiNNaker2, layers have to be split, mapped and scheduled onto 144 elements. We describe underlying mapping procedure with optimized data reuse achieve inference VGG-16 ResNet-50 models tens milliseconds.
The CPU-based system is widely used for simulating the brain-inspired spiking neural networks (SNN) by taking benefit of flexibility, while processing high input rates caused immature coding mechanism costs many CPU cycles, and introduction additional information required serial execution needs time-consuming pre- post-neuron matching algorithm. To address these issues, we propose an algorithm set leveraging multiply-accumulate (MAC) array to accelerate SNN inference. By rearranging...
The increasing density of Multiple-Input Multiple-Output (MIMO) arrays in imaging radars for the automotive industry demands highly parallel systems with low-footprint accelerators, which would enable concurrent processing a high number virtual channels low-latency, and without area overhead. In this paper, we design, implement, test multiple handcrafted compression schemes Twiddle Factor (TF) Read-Only Memories (ROM), aiming to reduce footprint variable-length dual-radix Fast Fourier...
With serial and parallel processors are introduced into Spiking Neural Networks (SNNs) execution, more researchers dedicated to improving the performance of computing paradigms by taking full advantage strengths available processor. In this paper, we compare integrate one SNN compiling system. For a faster switching between them in layer granularity, train classifier prejudge better paradigm before instead making decision afterwards, saving great amount time RAM space on host PC. The...
Industry leaders in automotive radars are moving towards highly dense MIMO (i.e., 4D radars), as they provide robust detection at a high angular resolution. However, these systems come the expense of parallel processing requirements, higher off- chip communication data rates, and power consumption result denser arrays to process. To date, no work open literature addresses low-power requirements DSPs for such FMCW radars, their scalability, on-chip Machine Learning (ML) context those azimuth,...
This live demo aims at continuously real-time classifying radar gesture signals from the real world with neuromorphic hardware SpiNNaker 2 prototype to play game. With 10 MHz operation frequency on FPGA, closed-loop setup realizes around 35 ms delay PC sending input data receiving classification output, and there is nearly no feeling of apparent when testers are playing The energy cost per frame 3.29 µJ, cycle less than 8 k. Even if our current middleware has not considered balanced work...
The potential low-energy feature of the spiking neural network (SNN) engages attention AI community. Only CPU-involved SNN processing inevitably results in an inherently long temporal span cases large models and massive datasets. This study introduces MAC array, a parallel architecture on each element (PE) SpiNNaker 2, into computational process inference. Based work single-core optimization algorithms, we investigate acceleration algorithms for collaborating with multi-core arrays. proposed...
In this work, the classification of walking direction based on ultrasonic signals has been examined for entrance counting. Feed-forward and recurrent neural network architectures as well simpler machine learning techniques have investigated compared with classical signal processing techniques.Using only a single receiver, focus was set development hardware-efficient system concept. Different measurement methods in time frequency domain perspective holistic energy optimization. The analysis...