The 3-2, 4-2 and 5-2 compressors are the basic components in many applications, particular partial product summation multipliers. In this paper novel architectures designs of high speed, low power capable operating at ultra-low voltages presented. consumption, delay area these new compressor compared with existing recently proposed shown to perform better. architecture lays emphasis on use multiplexers arithmetic circuits that result speed efficient design. Also all implementations XOR gate...

The 1-bit full adder is a very important component in the design of application specific integrated circuits. In this paper, authors propose three new adders having delay 2-transistor (2T) using existing XOR and XNOR gates. power consumption, area these are compared with ones results appear to be promising. combination low power, transistor count lesser makes viable option for efficient design.

In interconnect bus coding techniques the presence of buffers is often ignored. Buffers are used to restore signal level affected by parasitics. However have a certain switching time that contribute overall delay. Further transition happens in interconnects also crosstalk Thus delay due combined effect both buffer and Here replacement with Schmitt trigger has been proposed for same purpose restoration. Due lower threshold voltage can rise early large noise margin schmitt helps reducing...

Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3,2), (7,3), (15,4) (31,5) capable of operating at ultra-low voltages presented. Based on these counters, a generalized architecture is derived large (m, n) parallel counters. The proposed lays emphasis the use multiplexers combination CMOS transmission gate logic circuits that result speed efficient design. counter have been...

This paper presents a new improved multiplexer based decoder for flash analog-to-digital converters. The proposed is on 2:1 multiplexers. It calculates the binary code low operand length thermometer at initial stages and groups output of to generate final result. can be configured operate with reduced without any extra overhead. 'self-reconfigurable' property particularly useful in adaptive resolution Simulation results indicate that delay, power delay product when compared existing digital...

In VLSI interconnect buffers are used to restore the signal level affected by parasitics. However have a certain switching time that contributes overall delay. Further transitions occur in interconnects also contribute crosstalk Thus delay is due combined effect of both buffer and this work replacement with Schmitt trigger proposed for same purpose restoration. Due lower threshold voltage can rise early large noise margin helps reducing glitches as well. Simulation results shows approach...

In view of increasing prominence commercial, financial and Internet-based applications that process data in decimal format, there is a renewed interest providing hardware support to handle data. this paper, new architecture for efficient 1-digit addition binary coded (BCD) operands, which the core high speed multi-operand adders floating decimal-point arithmetic, proposed. Based on BCD adder, novel architectures higher order (n-digit) such as ripple carry adder look-ahead are derived. The...

The comparator is of paramount importance in many digital systems as it plays an important role almost all hardware sorters. In this paper, the design a 32-bit proposed based on logic parallel prefix adder. This circuit computes only final carry or borrow using structure modified adder and employs to compare two given numbers, thereby achieving latency O(log n). has been compared (both qualitatively quantitatively) with existing ones shown achieve efficiency 21% overall delay reduction 30% power.

Untrusted third parties and untrustworthy foundries highlighted the significance of hardware security in present-day world. Because globalization integrated circuit (IC) design flow semiconductor industry, issues must be taken to prevent intellectual property (IP) piracy. Logic encryption is an efficient method protect circuits from IP piracy, reverse engineering, malicious tampering IC for Trojan insertion. Researchers have proposed many logic methods, which lead overhead parameters such as...

This paper proposes novel approximate 4:2 compressors developed using input reordering circuits and combination probabilities. The circuit is used to reduce the hardware complexity of proposed designs. two designs compressors. compressor in designing an multiplier. multiplier utilize less energy than already published ones due acceptable inaccurate output/precision, which are best suitable for image processing applications. MUL1, MUL2, MUL3 MUL4 saves 22.75%, 21.95%, 11.57%, 8.95% existing design 1.

With the increasing prominence of commercial, financial and Internet-based applications that process data in decimal format, there is a renewed interest providing hardware support to handle such data. In this paper, novel efficient parallel architectures for 32-digit binary coded (BCD) multipliers are proposed using counters, BCD full adders converters. These counters have been designed used add partial products generated during multiplication product reduction tree. The architecture focuses...

An Incrementer/Decrementer (INC/DEC) is a common building block in many digital systems like address generation unit which are used microcontrollers and microprocessors. In this paper, novel architectures designs for binary gray INC/DECs presented faster than the existing ones without compromising terms of power. The proposed lay an emphasis on usage hybrid logic, that is, coupling transmission gate with CMOS gates at appropriate stages efficient design. Also, utilization output its...

Low power parallel array multiplier is proposed for both unsigned and two's complement signed multiplication. Modified Baugh-Wooley further modified if input numbers are not in form, method makes the calculation of number redundant, thus reducing delay. Also consumption has been found to be less than that multiplier.

This paper proposes an efficient approach to design high-speed, accurate multipliers. The proposed multiplier uses the 15:4 counter for partial product reduction stage. is designed using a novel 5:3 counter. input re-ordering circuitry at side. As result, number of output combinations can be reduced 18 from 32. circuit complexity reduces. and are on average 28% 19% improvement in power delay compared with existing designs. 16-bit counters 22.5%

Increasing prominence of commercial, financial and Internet-based applications, which process decimal data, there is an increasing interest in providing hardware support for such data. In this paper, new architecture efficient binary coded (BCD) adder/subtracter presented. This employs a method subtraction unlike the existing designs mostly use 10's complements, to obtain much lower latency. Though necessity correction some cases, delay overhead minimal. A complete discussion about cases...

The unexpected magnitude and scale of natural human-induced disasters have impelled the search rescue teams around world to seek for newer more innovative equipments enhance their efficiency. Earthquakes, Cyclones, tsunamis other leave terrain not only difficult navigation, but also dangerous human teams. Human are painfully slow sometimes need extreme caution. problem calls a fast effective rescuing system. Robots suddenly started seeking attention application in this field. This paper...

In this paper, a design for low power flash ADC with configurable resolution is proposed. A novel sub architecture employed to achieve variable as well switch the unused parallel voltage comparators and resistor bias circuit standby mode leading consumption of only leakage power. The capable operating at 4-bit, 6-bit 8-bit precision supply 1.0V, it consumes 48 mW 8-bit, 36 15 4-bit resolution. proposed have been designed, compared conventional verified post layout simulations in standard 65...

Decimal data processing applications have grown exponentially in recent years thereby increasing the need to hardware support for decimal arithmetic. In this paper, an improved architecture efficient Binary Coded (BCD) addition/subtraction is presented that performs binary without any extra hardware. The works both signed and unsigned numbers. design runtime reconfigurable maximum utilization of a feature architecture. Simulation results show proposed at least 32% better terms power-delay...

Summary Many of the modern deep learning, machine and artificial intelligence algorithms use adders, multipliers, multiply‐accumulators (MACs) with mixed precisions. In general, fixed‐point floating‐point MACs are used in mixed‐precision hardware, such that above algorithm can choose appropriate hardware for its processing. This paper proposes an efficient MAC circuit perform operations. The proposed design uses Han‐Carlson adder late carry or end‐around accumulator design; as a result,...

In floating point addition unit, adder and normalization decides the critical path delay. By predicting shift amount prior to adder's output delay introduced by can be reduced. This prediction is done using a technique called Leading Zero Anticipator (LZA). LZA algorithms are divided into exact inexact categories. Most of existing in nature which predicts with possible error 1 bit. So, these need an detection circuit. paper proposes logic implemented parallel part hardware resulting...

Approximate computing, which is an emerging technology aimed at improving the speed, power, and efficiency where precise computation not necessary. The paper proposes a new adder architecture that employs efficient method in least significant portion. Results demonstrate proposed achieves better accuracy than existing designs. Specifically, results show can provide up to 37.31% savings power when compared designs 55.3% improvement power-delay product. To validate efficacy of architecture,...