This letter proposes an unsigned approximate multiplier architecture segmented into three portions: the least significant portion that contributes to partial product (PP) is replaced with a new constant compensation term improve hardware savings without sacrificing accuracy. The PPs in middle are simplified using 4:2 compressor, and error due approximation compensated simple yet efficient correction module. most of implemented exact logic as approximating it will results large error....

Approximate computing is a promising method for designing power-efficient systems. Many image and compression algorithms are inherently error-tolerant can allow errors up to specific limit. In such algorithms, savings in power be achieved by approximating the data path units, as multiplier. This letter presents novel decoder logic-based multiplier design with intent reduce partial products generated. Thus, leading reduction hardware complexity consumption while maintaining low error rate....

Recent studies have demonstrated the potential for achieving higher area and power saving with approximate computation in error tolerant applications involving signal image processing. Multiplication is a major mathematical operation these which when performed logarithmic number system results faster energy efficient design. In this paper, authors present method combines Mitchell's approximation hardware truncation scheme novel way resulting an iterative multiplier improved precision area....

This paper presents a design of prefix grouping based reversible comparator. Reversible computing has emerged as promising technology having its applications in emerging technologies like quantum computing, optical etc. The proposed comparator consists three stages. first stage 1-bitcomparator where two outputs, gi indicating Ai > Bi and eiindicating = Bi, are generated for ith operand bits. outputs 1-bit grouped the second using final G A B E A=B generated. In last i.e. used to generate Lsignal

This paper presents a new improved multiplexer based decoder for flash analog-to-digital converters. The proposed is on 2:1 multiplexers. It calculates the binary code low operand length thermometer at initial stages and groups output of to generate final result. can be configured operate with reduced without any extra overhead. 'self-reconfigurable' property particularly useful in adaptive resolution Simulation results indicate that delay, power delay product when compared existing digital...

Approximate computing is an evolving paradigm that aims to improve the power, speed, and area in neural network applications can tolerate errors up a specific limit. This letter proposes new multiplier architecture based on algorithm adapts approximate compressor from existing proposed compressors' set reduce error respective partial product columns. Further, due approximation corrected using simple error-correcting module. Results prove power power–delay (PDP) of 8-bit improved by 39.9%...

An Increment/Decrement circuit is a common building block in many digital systems like address generation unit which are used micro controllers and microprocessors. Similarly 2's complement priority encoder circuits applications. This paper presents an improvement to the decision of existing INC/DEC architectures. results up 48% reduced delay 50% power product. also proposes reconfigurable INC/DEC/2's complement/Priority uses new proposed blocks.

Multiplication is an ubiquitous operation in growing set of media processing applications (graphics, audio, video, and image). Many these applications, however, possess inherent quality error resilience. Thus the multipliers, that are not very precise but return approximate value, can be utilized such applications. Such units, it may anticipated, result area savings while also resulting reduced power consumption. In recent years, logarithmic number system (LNS) has been increasingly used as...

Purpose Multipliers that form the basic building blocks in most of error-resilient media processing applications are computationally intensive and power-hungry modules. Therefore, improving multiplier’s performance terms area, critical path delay power has become an important research area. This paper aims to propose two improved multiplier designs based on a new approximate compressor circuit reduce hardware complexity at partial product reduction stage. The proposed 4:2 design...

Most image processing applications are naturally imprecise and can tolerate computational error up to a specific limit. In such applications, savings in power achieved by pruning the data path units, as an adder module. Truncation, however, may lead errors computing, therefore, it is always challenge between amount of that be tolerated application area, delay. This paper proposes segmented approximate reduce computation complexity error-resilient applications. The sub-carry generator aids...

Approximate computing, which is an emerging technology aimed at improving the speed, power, and efficiency where precise computation not necessary. The paper proposes a new adder architecture that employs efficient method in least significant portion. Results demonstrate proposed achieves better accuracy than existing designs. Specifically, results show can provide up to 37.31% savings power when compared designs 55.3% improvement power-delay product. To validate efficacy of architecture,...

This paper presents a twin precision multiplier with modified 2-D bypass Logic. The can perform one 8-bit multiplication or two 4-bit multiplications. structure is by adding 2-dimensional bypassing logic resulting in reduction dynamic power as well the delay. Simulation results indicate that marginal increase area, proposed achieves an improvement of 25.5% delay and up to 29% power-delay product when compared existing designs.

Reversible computing has emerged as promising technology having its applications in quantum computing, nanotechnology and optical computing. This paper presents design analysis of reversible ripple, prefix ripple hybrid adders. Firstly an comparison all the existing carry adders is presented. The are characterized by high depth, low cost and/or garbage outputs ancilla inputs bits. Secondly methodology for Finally proposed prefix-ripple presented different parameters illustrated.

The need to have hardware support for decimal arithmetic is increasing in recent years because of the growth data processing commercial, financial and internet based applications. In this paper a new architecture efficient Binary coded (BCD) addition/subtraction presented that can be reconfigured perform binary addition/subtraction. mainly designed, keeping mind signed magnitude format. proposed avoids usage additional 2's complement 10's circuitry, correcting results sign run-time...

Approximate computing is an emerging paradigm to achieve substantial improvement in the area, speed, and power image processing applications where exact computation not required. This paper proposes new approximate unsigned multiplier architectures which aim reduce consumption area with better accuracy. For 8-bit scheme, experimental results show of 41.4% 34.02% respectively, when proposed design compared against design, 22.88% 26.72% respectively other designs, without compromising on

This paper presents a Reconfigurable Parallel Prefix Ling Adder. The proposed design can be partitioned to perform as one 16 bit, two 8 bit and four 4 adders. We also propose new architecture for Enhanced Flagged Binary Adder (EFBA) designs which reduces the delay of operation considerably. adders are, therefore, modifications conventional Carry Lookahead (CLA) - EFBA arrangements. estimate reduction 6.8% in critical path with respect traditional implementation CLA-EFBA logic. architectures...