The paper presents a prototype integrated circuit built in 40 nm CMOS process for readout of hybrid pixel detector. core the IC constitutes matrix 18 ×24 pixels with size 100 μm ×100 μm. explains functionality and architecture IC, which is designed to operate both standard single photon counting mode interpixel communication mitigate negative effects charge sharing. This article focuses on measurement results operating mode. measured ENC 84e <sup...

This brief presents the design and measurement results of a prototype SPHIRD-1 ASIC in CMOS 40 nm process. The chip is dedicated to high count rate single photon counting operation at European Synchrotron Radiation Facility with Extremely Brilliant Source. core IC matrix <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$64\times32$ </tex-math></inline-formula> pixels notation="LaTeX">$50 \mu \text{m}$ pitch....

We report on the design of a 128-channel ASIC named STS-XYTER (Silicon Tracking System - X Y Time -Energy Read-out) dedicated for signal detection from doublesided silicon microstrip sensors with high capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DET</sub> ≈ 30 pF). The contains: 128 charge processing channels, calibration unit, biasing circuitry based built-in band-gap reference source and full digital back-end, which provides...

We present the design and measurements of a novel 64 channel ASIC dedicated for recording stimulation neural network activity. Chip is designed in submicron CMOS 180nm technology, occupies 5×5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> silicon area, consumes only 25 μW/channel. The low cut-off frequency can be tuned range 60 mHz-100 Hz while mean high 4.7 kHz or 12 kHz. voltage gain may also changed. Mean measurement values show...

This paper presents an implementation of asynchronous approximation a center gravity binary object on focal plane pixel detector. The direct field its application is dealing with charge sharing in processing signals from semiconductor X-ray hybrid detectors. developed algorithm called the temporal (COGITO), standing for geometrical COGITO that cloud sampled by Its operation resembles image finding image. presented circuitry operates entirely digital domain-the analog front end not included....

We report on the design of a self-triggered analog front-end readout electronics dedicated for signal detection from double-sided silicon microstrip sensors with capacitance at order tens pF (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DET</sub> ≈ 30 pF). The main requirements are: processing input pulses average rate 150 kHz/channel, low power consumption and noise same time. single channel is built two different parallel chains: fast...

This work presents design and measurement results of FRIC—a prototype ROIC for fine resolution hybrid pixel detectors. The chip was manufactured in 40 nm CMOS process contains an array 64 × pixels with 50 μm pitch. It implements a very versatile analog front-end, capable energy 0.71 keV FWHM estimated dead-time ns. also features Pattern Recognition algorithm together signal summing charge sharing correction. Low power consumption makes this circuit applicable large-area

Abstract This paper presents a readout integrated circuit (IC) of pixel architecture called MPIX (Multithreshold PIXels), designed for CdTe detectors used in X-ray imaging applications. The IC area is 9.6 mm × 20.3 and it CMOS 130 nm process. core matrix 96 192 square-shaped pixels 100 µm pitch. Each contains fast analog front-end followed by four independently working discriminators 12-bit ripple counters. Such allows photon processing one selecting the photons according to their energy...

Charge sharing is the fractional collection of charge cloud generated in a detector by two or more adjacent pixels. It may lead to excessive inefficient registration hits comparing number impinging photons depending on how discrimination thresholds are set typical photon counting pixel detector. The problems particularly exposed for fine sizes and/or thick planar detectors. Presence one limiting factors that discourages decreasing pixels mode X-ray radiation imaging systems. Currently, few...

A 64-channel Neuro-Stimulation-Recording chip named NRS64 for neural activity measurements has been designed and tested. The occupies 5×5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of silicon area consumes only 25 μW/channel. low cut-off frequency can be tuned in the 60 mHz - 100 Hz range while a high set to 4.7 kHz or 12 kHz. voltage gain 139 V/V 1100 V/V. measured input referenced noise is 3.7 μV rms band 7.6 3 band. digital...

Thanks to the detector technology development based on high Z materials (GaAs, CdTe, CZT, etc.), hybrid pixel detectors with direct photon-to-charge conversion become more and popular, even in medical applications. Single photon counting systems aim at good position resolution, so making a size smaller is general tendency such systems. However, for pitch of about 100 μm charge division effect becomes visible it affects up 20–30% all interactions, depending thickness bias voltage. For this...

The design and measurement results of a micro-power successive approximation charge redistribution ADC implemented in CMOS 180 nm technology are presented. project has been optimized for very low area occupancy order to utilize it multichannel neural signal recording pixel systems future application. fabricated, experimentally characterized exhibits good performance, especially from the silicon occupation point view. presented converter achieves 500 kS/s sampling rate with ENOB 6.54 at 4.45...

Abstract This paper presents the design and simulation of a prototype chip in CMOS 40 nm process for high spatial resolution operation at ESRF-EBS synchrotron. The core IC is pixel matrix with 50 µm pitch, operating single photon counting mode. Each contains Charge Sensitive Amplifier (CSA) fast discharge block detector leakage current compensation circuit. CSA output directly connected to discriminator an offset trimming capability. optimized monochromatic X-ray beam energy up 30 keV....

Abstract We present the design of an in-pixel artificial intelligence (AI) for extraction amplitude a pulse generated in semiconductor detector. The AI is with traditional multi-level perceptron scheme having 6 layers and total number 420 parameters. implementation shows 0.34% measurement accuracy. block fed by 6-bit ADC at 5 MHz sampling rate. Standard front-end optimized low-noise pulses carrying 1000–3000 electrons. methodology was tested using FPGA results are promising. intended to be...

This paper presents multi-objective optimization of a front-end electronics implemented in multichannel integrated circuit for silicon sensors readout the Silicon Tracking System CBM experiment at FAIR center. We present towards low-power (<; 8 mW/channel) and low-noise while keeping channel pitch 58 μm minimum number external components required circuit's operation. Detailed study system noise (equivalent charge) with respect to realistic model detector interconnecting kapton microcable as...

Hybrid pixel detectors, operating in a single photon counting mode provide noiseless imaging, good spatial resolution and adjustable energy thresholds. Decreasing size allows operation with fluxes of higher intensities. However, decreasing pitch, detector suffers more significantly from charge sharing. Therefore, various algorithms are implemented on-chip to mitigate sharing effect prevent the counts loss. Nonetheless, if algorithm dealing is implemented, dead time increases. The aim this...

The SPHIRD project is a study towards the development of new generation X-ray photon counting pixel detectors for synchrotron radiation applications operating between 10 and 35 keV, with very high count rate capabilities small pixels. relies on design construction test prototypes complemented by detector simulations. strategy to boost consists in combining fast analog front-end pile-up compensation techniques option binning. intends explore compare different time-based amplitude-based...

Abstract As a follow-up of Signal-to-Noise Ratio (SNR) study presented previously, this work discusses the experimental results obtained for statistical analysis photon counting detector measurements. The test device is hybrid assembly built with pixelated 400 μm thick electron collection Si sensor bump-bonded to SPHIRD readout ASIC. analog front-end in each pixel ASIC produces pulse tens nanoseconds X-ray hit, and its digital circuitry implements both amplitude time-based pile-up...