A5105889257- Particle Detector Development and Performance
- CCD and CMOS Imaging Sensors
- Radiation Detection and Scintillator Technologies
- Neutrino Physics Research
- Particle physics theoretical and experimental studies
- Dark Matter and Cosmic Phenomena
- Advanced Semiconductor Detectors and Materials
- 3D IC and TSV technologies
- Astrophysics and Cosmic Phenomena
- Advancements in Semiconductor Devices and Circuit Design
- Analog and Mixed-Signal Circuit Design
- Semiconductor materials and devices
- Advanced X-ray and CT Imaging
- Atomic and Subatomic Physics Research
- Radiation Effects in Electronics
- Advancements in PLL and VCO Technologies
- Advanced Memory and Neural Computing
- Advanced Data Storage Technologies
- Nuclear Physics and Applications
- Medical Imaging Techniques and Applications
- Parallel Computing and Optimization Techniques
- Network Packet Processing and Optimization
- Advanced Optical Sensing Technologies
- Photonic and Optical Devices
- Distributed and Parallel Computing Systems
Brookhaven National Laboratory
2006-2024
Brookhaven College
2024
Fermi National Accelerator Laboratory
2012-2021
AGH University of Krakow
2003-2020
Fermi Research Alliance
2013-2019
Istituto Nazionale di Fisica Nucleare, Sezione di Torino
2019
European Organization for Nuclear Research
2019
Science and Technology Facilities Council
2019
Rutherford Appleton Laboratory
2019
Special Olympics
2013
A monolithic active pixel sensor (MAPS) for charged particle tracking based on a novel detector structure has been proposed, simulated, fabricated and tested. This is inseparable from the readout electronics, since both of them are integrated same, low-resistivity silicon wafer standard CMOS process. The individual comprised only three MOS transistors photodiode collecting charge created in thin undepleted epitaxial layer. approach provides low cost, high resolution device with whole area...
Abstract A low-power integer- N frequency synthesizer for flexible on-chip clock generation has been designed in a 65 nm CMOS process. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and 3 GHz that are locked 10–50 reference input. design uses phase-locked loop (PLL) with dual-tuned LC voltage-controlled oscillator (VCO), programmable feedback divider, dual output dividers. total power consumption from 1.2 V 0.8 supplies is 4.0 mW. Experimental...
Abstract Building on a prototype readout integrated circuit for segmented silicon sensors with the EDWARD event-driven architecture, front-end in each pixel was replaced by hardware generator to verify performance, ensuring no data loss, consistent priority handling, and speed verification. This produces Poisson-distributed requests individually tunable rates per via digitally controlled oscillator. The resulting EDWARD65P1 test ASIC is 32×32 matrix 100 μm pitch, equipped digital event...
The choice between cold and warm electronics (inside or outside the cryostat) in very large LAr TPCs (>5-10 ktons) is not an issue, but it rather a major cryostat design issue. This because location of signal processing has direct far reaching effect on design, indirect TPC electrode (sense wire spacing, length drift distance), significant performance. All these factors weigh so overwhelmingly favor that remains optimal solution for TPCs. In this paper noise considerations are summarized,...
The paper presents a prototype integrated circuit built in 40 nm CMOS process for readout of hybrid pixel detector. core the IC constitutes matrix 18 ×24 pixels with size 100 μm ×100 μm. explains functionality and architecture IC, which is designed to operate both standard single photon counting mode interpixel communication mitigate negative effects charge sharing. This article focuses on measurement results operating mode. measured ENC 84e <sup...
The Deep Underground Neutrino Experiment will use unsurpassed quantities of liquid argon to fill a time projection chamber. Research is under way place the electronics inside cryostat. For reasons efficiency and economics, lifetimes these circuits must be well in excess 20 years. principle mechanism for lifetime degradation MOSFET devices operating at cryogenic temperatures hot carrier degradation. It therefore imperative that studies performed candidate technologies explore determine if...
The Vertically Integrated Photon Imaging Chip (VIPIC) project explores opportunities of the three-dimensional integration for imaging X-rays. design details VIPIC1 chip are presented and followed by results testing chip. was designed in a 130 nm process, which through silicon vias embedded right after front-end-of-line processing. tiers is achieved Cu-Cu thermo-compression or Cu-based oxide-oxide bonding. readout integrated circuit high timing resolution, pixel based, X-ray Correlation...
In order to develop precision vertex detectors for the future linear collider, fast monolithic active pixel sensors are studied. A standard CMOS 0.25 /spl mu/m digital process is used design a test chip which includes different types, column-level discriminators, and fully programmable sequencer. In-pixel amplification implemented together with double sampling. Different charge-to-voltage conversion factors were obtained using amplifiers gains or diode sizes. Pixel architectures dc ac...
The exploration of vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab 2006. This paper examines the opportunities that vertical integration offers by looking various 3D designs have been completed Fermilab. emphasis is on are presented through silicon vias (TSV), wafer and circuit thinning, finally fusion bonding techniques to replace conventional bump bonding. Early work has led an international consortium...
The vertically integrated photon imaging chip (VIPIC1) pixel detector is a stack consisting of 500-μm-thick silicon sensor, two-tier 34-μm-thick circuit, and host printed circuit board (PCB). tiers were bonded using the direct bonding technology with copper, each tier features 1-μm-diameter throughsilicon vias that used for connections to sensor on one side, PCB other side. 80-μm-pixel-pitch was nickel circuit. mounted Sn-Pb balls placed 320-μm pitch, yielding an entirely wire-bond-less...
Small-angle scattering X-ray photon correlation spectroscopy (XPCS) studies were performed using a novel photon-counting pixel array detector with dual counters for each pixel. Each counter can be read out independently from the other to ensure there is no readout dead-time between neighboring frames. A maximum frame rate of 11.8 kHz was achieved. Results on test samples show good agreement simple diffusion. The potential extending time resolution XPCS beyond limit set by also discussed.
Abstract Data bandwidth, timing resolution and resource utilization in readouts of radiation detectors are a constant challenge. Event driven solutions pushing against well-trenched framed solutions. The idea for an asynchronous readout architecture called EDWARD ( E vent- D riven W ith A ccess R eset ecoder) was presented at the TWEPP 2021 conference. Here we show progress our work which resulted two chip prototypes. first one, named 3FI65P1, is full device with analog pixel circuitry...
We report on the performance of MIMOSA8 (HiMAPS1) chip. The chip is a 128times32 pixels array where 24 columns have discriminated binary outputs and eight analog test outputs. Offset correction techniques are used extensively in this to overcome process related mismatches. divided four blocks with different conversion factors controlled by serially programmable sequencer. representative CMOS sensors development option considered as promising candidate for Vertex Detector future International...
This paper presents the detailed characterization of a single photon counting chip, named CHASE Jr., built in CMOS 40-nm process, operating with synchrotron radiation. The chip utilizes an on-chip implementation C8P1 algorithm. algorithm eliminates charge sharing related uncertainties, namely, dependence number registered photons on discriminator's threshold, set for monochromatic irradiation, and errors assignment event to certain pixel. article short description as well architecture chip....
We report on the design of an active feedback circuit for charge sensitive amplifiers used reading out hybrid pixel detectors. The predominant advantages proposed over existing solutions are its low noise, stability, and tunability. In addition, occupies small silicon area, which is crucial This paper presents both mathematical analysis measurement results obtained with test structure.