A5005121336- Radio Frequency Integrated Circuit Design
- Particle Detector Development and Performance
- Error Correcting Code Techniques
- Ultra-Wideband Communications Technology
- Advancements in PLL and VCO Technologies
- Advanced Wireless Communication Techniques
- Advancements in Semiconductor Devices and Circuit Design
- Radiation Effects in Electronics
- Analog and Mixed-Signal Circuit Design
- Radiation Detection and Scintillator Technologies
- Antenna Design and Analysis
- Microwave Engineering and Waveguides
- CCD and CMOS Imaging Sensors
- Semiconductor materials and interfaces
- Quantum Dots Synthesis And Properties
- Semiconductor materials and devices
- Advanced Data Storage Technologies
- Chalcogenide Semiconductor Thin Films
- Cellular Automata and Applications
- Distributed and Parallel Computing Systems
- Low-power high-performance VLSI design
- Parallel Computing and Optimization Techniques
- Electromagnetic Compatibility and Noise Suppression
- Telecommunications and Broadcasting Technologies
- Gyrotron and Vacuum Electronics Research
Fermi National Accelerator Laboratory
2024
University of Padua
2011-2023
Istituto Nazionale di Fisica Nucleare, Sezione di Padova
2016-2019
Engineering (Italy)
2012
Polytechnic University of Turin
2006
This paper presents a fully integrated UWB-IR transceiver front-end operating in the 7.25-8.5 GHz band designed for high overall transmission and detection energy efficiency robustness to interferers. The features pulsed transmitter that wakes up when triggered by digital signal, generates pulse, automatically switches-off less than 2 ns. receiver includes an LNA, VGA, squarer, windowed integrator, comparator perform PPM demodulation of data. A prototype was 0.13 μm CMOS technology. delivers...
This study proposes an energy detector for a noncoherent impulse-radio UWB receiver, designed in 0.18-mum CMOS technology. The squaring functionality is realized exploiting the quadratic characteristic of MOS transistors, and deviation from such due to short channel effects device mismatch carefully considered paper. squared signal integrated using Gm-C integrator that interfaced with squarer flipped voltage follower current sensor as converter. proposed circuit dissipates 5.4 mW receiver...
Abstract The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 × μm 2 pixels for the HL-LHC upgrades of ATLAS and CMS experiments at CERN. A common architecture, design verification framework been to enable final different sizes be designed, verified tested handle extreme hit rates 3 GHz/cm (up 12 GHz per chip) together an increased trigger rate 1 MHz efficient readout up 5.12 Gbits/s chip. Tolerance extremely hostile radiation environment Grad over 10 years...
This work presents the design and test results of an analog decoder for 40-bit block length, rate 1/3, Turbo Code defined in UMTS standard. The prototype is fully integrated a three-metal double-poly 0.35-/spl mu/m CMOS technology, includes I/O interface that maximizes throughput. After successful implementation proof-of-concept iterative decoders by different research groups both bipolar technologies, this first reported realistic error-correcting code. was successfully tested at maximum...
This paper is a review of recent progress RD53 Collaboration. Results obtained on the study radiation effects 65 nm CMOS have matured enough to define first strategies adopt in design analog and digital circuits. Critical building blocks very front end chains been designed, tested before after 5–800 Mrad. Small prototypes 64×64 pixels with complex architectures produced, point address main issues dealing extremely high pixel rates, while operating at small in-time thresholds end. The...
An energy detector designed in a 0.18μm CMOS technology and intended for non-coherent impulse-radio UWB receiver is presented this paper. The proposed circuit exploits the quadratic current characteristic of saturated MOS transistors to square input pulses that cover whole bandwidth. integral computed with Gm-C architecture connected squarer using flipped voltage follower sensor. A behavioural model developed order put perspective complete system translate transistor-level figures merit...
In this work we present a full analog turbo decoder for hard-disk EPR-IV read channels in CMOS technology. The design is based on current-mode approach developed by Loeliger et al. [2001], the implementation of sum-product algorithms. circuit's main attractions are coding gain offered codes over uncoded channel, and relative simplicity power efficiency digital approach. circuit 0.18 /spl mu/m technology operates at 1.8 V supply, with total simulated consumption (including peripheral...
The design and test results of a three-metal, double-poly, 0.35 μm; CMOS analog turbo decoder for the rate-1/3, block length 40, UMTS code, are presented. A discrete-time model decoding networks is also This can be used as tool to both predict chip performance in short time give guidelines complex decoders, which circuit-level simulations impractical.
The Phase 2 upgrades of silicon pixel detectors at HL-LHC experiments feature extreme require- ments, such as: 50x50 μm pixels, high rate (3 GHz/cm2), unprecedented radiation levels (1 Grad), readout speed and serial powering. As a consequence new chip is required. In this framework the RD53 collaboration submitted RD53A, large scale demonstrator de- signed in 65 nm CMOS technology, integrating matrix 400×192 pixels. It features design variations analog digital for testing purposes. An...
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">In this paper, we present an all-analog implementation of the rate-1/3, block length 40, universal mobile telecommunications system (UMTS) turbo decoder. The prototype was designed and fabricated in 0.35 <formula> <tex>$\mu$</tex> </formula>m complementary metal-oxide-semiconductor technology operates at 3.3 V. We also introduce a discrete-time first-order model for analog decoders which allows...
RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm$^2$) and radiation levels (500 Mrad, possibly 1 Grad) ATLAS CMS phase 2 upgrades. It features serial powering operation design variations in analog digital matrix different testing purposes. The verification of are described together with an outline plans to develop final chips two experiments.
The increasing interest in impulse radio UWB communication links focuses the research on building blocks optimized for these specific systems. In this context, paper proposes a ring oscillator an transmitter. A multiloop is considered because it holds potential of both high oscillation frequency and fast switch-on time. novelty proposed inverter cell found possibility to adjust digitally, rather than with analog voltage. This leads larger tuning range less sensitivity control noise....
The RD53 collaboration is developing a large scale pixel front-end chip, which will be tool to evaluate the performance of 65 nm CMOS technology in view its application readout innermost detector layers ATLAS and CMS at HL-LHC. Experimental results characterization small prototypes discussed frame design work that currently leading development demonstrator chip RD53A submitted early 2017. paper focused on analog processors developed framework collaboration, including three time over...
This paper presents an ultra-wideband impulse radio (UWB-IR) receiver (RX) for ultralow energy consumption applications. The design of the takes full advantage pulsed nature UWB-IR communication technology aiming at architectural simplicity, avoidance precise frequency reference generation, and symbol-level duty-cycled operation. tradeoff between sensitivity energy-per-bit is briefly addressed different options taken into consideration. A prototype was fabricated in 130-nm CMOS tested....
This paper presents a fully integrated UWB-IR transceiver front end operating in the 7.25-8.5 GHz band designed for high overall transmission and detection energy efficiency robustness to interferers. The features pulsed transmitter that wakes up when triggered by digital signal, generates pulse, automatically switches-off less than 2ns. receiver includes an LNA, VGA, squarer, windowed integrator, supports OOK PPM modulation. A prototype of was 130 nm CMOS technology. delivers 13 pJ/pulse...
The RD53A large scale pixel demonstrator chip has been developed in 65 nm CMOS technology by the RD53 collaboration, order to face unprecedented design requirements of 2 phase upgrades CMS and ATLAS experiments at CERN. This prototype is designed demonstrate that a set challenging specifications can be met, such as: high granularity (small pixels 50×50 or 25× 100 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) size (~2×2 cm ), hit...
This work discusses the design and main results relevant to characterization of analog front-end processors in view their operation pixel detector readout chips ATLAS CMS at High-Luminosity LHC. The channels presented this paper are part RD53A, a large scale demonstrator designed 65 nm CMOS technology by RD53 collaboration. collaboration is now developing full-sized for actual experiments. Some details on improvements implemented front-ends provided paper.
The use of a reactive passive mixer is proposed to implement an efficient Cartesian transmitter for IoT applications, capable supporting high-order modulations, and high data rates. Prototypes in 22 nm FD-SOI CMOS technology show 5.5 dBm output-referred 1 dB compression point with 34.1% system efficiency CW operation. Under 2.4 Mbaud, 16-QAM modulation at 2.7 average output power, they achieve 9.6 Mb/s rate, EVM = −24.5 dB, ACLR −32 dBc, P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML"...
In this paper, the design of a fully analog iterative decoder for serially concatenated convolutional code is presented. The reconfigurable in both block length and rate. An interleaver size up to 2400 bit considered. core implements single SISO working on window whole trellis. It then reused several times decode two constituent codes. resulting performs iterations, but it analog. extrinsic information exchanged decoding process stored an memory permuted through interleaver. Behavioral...
Trellis coded modulation (TCM) is a potential candidate for error correction in multilevel flash memories. TCM typically requires probabilistic decoding algorithms (e.g. BCJR), that can be conveniently implemented the analog domain. In this work, we study feasibility and complexity of approach, proposing transistor-level solutions building blocks decoder. case designed an effective storage density 3 information bits/cell, decoder 196-bit field features estimated current draw <0.5 mA area...
A non-coherent 130nm CMOS UWB impulse radio receiver for ultra-low energy consumption applications is presented. The supports a 4.4 Mb/s data rate employing 2-PPM modulation, with sensitivity of 0.57 aJ. Implementing symbol-level duty-cycling, such an outstanding performance attained at only 440 pJ/b.
After having long been used in military radio applications, Ultra-Wideband Impulse Radio (UWB-IR) is now emerging as a communication technology suitable for short-range, low data-rate links applications with tight energy budget. As significant example of this trend, work we will present fully integrated UWB-IR transceiver front-end operating the 7.25 - 8.5 GHz band designed high overall transmission and detection efficiency robustness to interferers. The results that be reported give...
In this paper, we discuss the design and testing results of an analog 0.35 /spl mu/m CMOS turbo decoder for rate-1/3, 40 bit UMTS code. The prototype was successfully tested at nominal conditions (2 Mbit/s), with overall power consumption 10.3 mW 3.3 V. BER curve shows a limited performance loss (about 0.5 dB) respect to that digital implementation. We also discrete-time model which allows us run simulations including circuit transient behavior device mismatch in very short time....