F. De Canio
A5070940935- Particle Detector Development and Performance
- Advancements in Semiconductor Devices and Circuit Design
- Radiation Effects in Electronics
- Radiation Detection and Scintillator Technologies
- CCD and CMOS Imaging Sensors
- Analog and Mixed-Signal Circuit Design
- Advancements in PLL and VCO Technologies
- Low-power high-performance VLSI design
- Advanced Data Storage Technologies
- Particle physics theoretical and experimental studies
- Radio Frequency Integrated Circuit Design
- Interconnection Networks and Systems
- VLSI and Analog Circuit Testing
- Advanced Memory and Neural Computing
- Network Packet Processing and Optimization
- Cellular and Composite Structures
- 3D IC and TSV technologies
- Semiconductor materials and devices
- Silicon and Solar Cell Technologies
- Electromagnetic Compatibility and Noise Suppression
- Parallel Computing and Optimization Techniques
- Electrostatic Discharge in Electronics
- Advanced Numerical Analysis Techniques
- Atomic and Subatomic Physics Research
- Nuclear Physics and Applications
Istituto Nazionale di Fisica Nucleare, Sezione di Pavia
2015-2020
University of Bergamo
2016-2020
University of Pavia
2015-2019
Abstract The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 × μm 2 pixels for the HL-LHC upgrades of ATLAS and CMS experiments at CERN. A common architecture, design verification framework been to enable final different sizes be designed, verified tested handle extreme hit rates 3 GHz/cm (up 12 GHz per chip) together an increased trigger rate 1 MHz efficient readout up 5.12 Gbits/s chip. Tolerance extremely hostile radiation environment Grad over 10 years...
Pixel detectors at HL-LHC experiments or other future are facing new challenges, especially in terms of unprecedented levels radiation and particle flux. This paper describes the progress made by CHIPIX65 project INFN for development a generation readout ASIC using CMOS 65 nm technology.
This paper is a review of recent progress RD53 Collaboration. Results obtained on the study radiation effects 65 nm CMOS have matured enough to define first strategies adopt in design analog and digital circuits. Critical building blocks very front end chains been designed, tested before after 5–800 Mrad. Small prototypes 64×64 pixels with complex architectures produced, point address main issues dealing extremely high pixel rates, while operating at small in-time thresholds end. The...
This work is concerned with the design and experimental characterization of analog front-end electronics conceived for experiments unprecedented particle rates radiation levels at future high-energy physics colliders. A prototype chip integrating different test structures has been submitted in framework CHIPIX65 project. These are standalone channels readout hybrid pixels, featuring a charge sensitive preamplifier as first stage chain, high-speed comparator circuit fine threshold tuning. The...
A radiation-hard BGR (bandgap voltage reference) circuit is here presented. It's able to maintain the output accuracy over process, voltage, and temperature (PVT) variations, combined with extremely high total-ionizing-dose (up 800 Mrad (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )), as required by next experiments upgrades of Large Hadron Collider (LHC). The design has been dealt starting from several experimental results,...
A front-end channel prototype for pixel detectors has been designed the upgrades of HL-LHC experiments.The circuit is based on a Krummenacher feedback network to continuously reset charge sensitive amplifier and fast threshold discriminator implement time-over-threshold (ToT) method perform amplitude measurement.The frontend was developed in 65 nm CMOS technology takes an overall area not exceeding 1250 µm 2 , i.e., half area.The current consumption per around 4 µA at V DD = 1.2 V.A very...
This work presents the design of a low-power, differential signaling, input/output data link in 65 nm CMOS process for high energy physics (HEP) experiments. The proposed driver, able to operate at 320 Mbps or 640 with normalized power dissipation 3.125 mW/Gbps, is meant drive short distance (between 2 and 10 cm) transmission lines located module hybrid circuit. A de-emphasis technique has been adopted reduce impedance mismatch effects between driver output line. paper will discuss detail...
This paper presents the design of a LVDS input/output interface circuit for next generation Associative Memory (AM) chip. The bandwidth Memories is critical aspect that needs to be addressed in order increase number comparisons per second. Our aim transfer parallel buses at 500 MHz. Since large receivers/drivers will included AM chip, power consumption circuits has been taken into account. discussed this work submitted fabrication December 2016 28 nm CMOS technology.
This paper describes a readout ASIC prototype designed by CHIPIX65 project, part of RD53, for pixel detector at HL-LHC . A 64 × matrix 50 μ m2 pixels is realised. digital architecture has been developed, with particle efficiency above 99.9% 3 GHz/cm2 rate, 1 MHz trigger rate 12.5 s latency. Two analog front end designs, one synchronous and asynchronous, are implemented. Charge measured 5-bit precision the dead-time below 1%. IP-blocks (DAC, ADC, BandGap, SER, sLVS-TX/RX) very ends silicon...
This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for pixel detector at HL-LHC . A 64×64 matrix 50×50μm2 pixels is realised. digital architecture has been developed, with particle efficiency above 99.5% 3 GHz/cm2 rate, trigger frequency 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous asynchronous, are implemented. Charge measured 5-bit precision, dead-time below 1%. The chip integrates first time many components developed...
This paper presents the characterization of new Associative Memory chip (version 7) designed and fabricated in 28 nm CMOS. The design aims at: enhancing links from/to FPGAs; increasing bandwidth thanks to full custom LVDS transceivers; reducing power consumption silicon area by means memory cells with full-custom approach. was submitted December 2016; prototypes were packaged a 17 × Ball Grid Array (BGA) standalone package. Prototype confirms functionality. final will be assembled System In...
In this paper we present a new Associative Memory (AM) chip designed in the 28 nm TSMC HPL technology. Two of main characteristics are reduced power consumption and an increased memory cell area density by use two newly technologies. The aim is to test technologies with realistic front-end functions. integration AM FPGA also enhanced. addition, LVDS drivers receivers implemented strengthen signal integrity I/Os. design submitted for fabrication. die will be packaged 17 × Ball Grid Array...
This paper presents the characterization of an input/output interface circuit designed for multi-purpose pattern recognition applications compatible with low-voltage fully differential signaling (LVDS) standard. The driver and receiver circuits described in this work has been fabricated a 28 nm CMOS technology. prototype chip mounted on printed board physical characteristics similar to real application case validated up 1 Gb/s input random patterns.
This work is concerned with the design and characterization of bandgap reference circuits capable operating a power supply 1.2 V in view applications to HL-LHC experiments. Due harsh environment foreseen for these devices, different solutions have been considered implemented 65 nm CMOS technology. Together conventional structure which exploits bipolar smaller solution based on pn diodes version MOS transistors biased weak inversion region are included. paper intends describe compare features...
The upgrade of the CMS tracker at HL-LHC relies on hybrid modules built high density interconnecting flexible circuits. They contain several flip chip readout ASICs having speed digital ports required for configuration and data readout, implemented as customized Scalable Low-Voltage Signalling (SLVS) differential pairs. This paper presents connectivity requirements hybrids; it compares transmission line implementations in terms board area, achievable impedances expected crosstalk. properties...
RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm$^2$) and radiation levels (500 Mrad, possibly 1 Grad) ATLAS CMS phase 2 upgrades. It features serial powering operation design variations in analog digital matrix different testing purposes. The verification of are described together with an outline plans to develop final chips two experiments.
A front-end channel prototype for pixel detectors has been designed the upgrades of HL-LHC experiments. The circuit is based on a Krummenacher feedback network to continuously reset charge sensitive amplifier and fast threshold discriminator implement time-over-threshold (ToT) method perform amplitude measurement. was developed in 65 nm CMOS technology takes an overall area not exceeding 25 μm×50 μm. power dissipation per channel, including dynamic consumption, around 5 μW. This paper...
The RD53 collaboration is developing a large scale pixel front-end chip, which will be tool to evaluate the performance of 65 nm CMOS technology in view its application readout innermost detector layers ATLAS and CMS at HL-LHC. Experimental results characterization small prototypes discussed frame design work that currently leading development demonstrator chip RD53A submitted early 2017. paper focused on analog processors developed framework collaboration, including three time over...
This paper discusses the main results relevant to characterization of an analog front-end processor designed in view experiments with unprecedented particle rates and radiation levels at high-luminosity Large Hadron Collider (HL-LHC). The channel presented this is part CHIPIX65-FE0 prototype, a readout application-specified integrated circuit 65-nm CMOS technology frame CERN RD53 collaboration. prototype integrates 64 × pixel matrix, divided into two 32 submatrices, featuring squared pixels...
A first prototype of a readout ASIC in CMOS 65 nm for pixel detector at High Luminosity LHC is described. The cell area 50×50 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the matrix consists 64×64 pixels. chip was designed to guarantee high efficiency extreme data rates very low signals with power consumption. Two different analogue front-end designs, one synchronous asynchronous, were implemented, both occupying an 35×35 . ENC...
A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part the Italian INFN CHIPIX65 project using commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to CHIPIX-FE0, is composed matrix 64 x pixels with 50$\mu$m size embedding two different architectures analog front-ends working in parallel. The final layout chip was submitted accepted for fabrication on July 2016. Chips were received...
The RD53A large scale pixel demonstrator chip has been developed in 65 nm CMOS technology by the RD53 collaboration, order to face unprecedented design requirements of 2 phase upgrades CMS and ATLAS experiments at CERN. This prototype is designed demonstrate that a set challenging specifications can be met, such as: high granularity (small pixels 50×50 or 25× 100 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) size (~2×2 cm ), hit...