A5044855375- 3D IC and TSV technologies
- Photonic and Optical Devices
- Additive Manufacturing and 3D Printing Technologies
- Semiconductor Lasers and Optical Devices
- Particle Detector Development and Performance
- CCD and CMOS Imaging Sensors
- Parallel Computing and Optimization Techniques
- Semiconductor materials and devices
- Thin-Film Transistor Technologies
- Interconnection Networks and Systems
- Advanced Photonic Communication Systems
- Electronic Packaging and Soldering Technologies
- Optical Network Technologies
- Manufacturing Process and Optimization
- Electrowetting and Microfluidic Technologies
- Advanced Memory and Neural Computing
- Advanced Data Storage Technologies
- Photonic Crystals and Applications
- Heat Transfer and Optimization
- Radiation Detection and Scintillator Technologies
- Radiation Effects in Electronics
- Advanced MEMS and NEMS Technologies
- Electrical and Thermal Properties of Materials
- Copper Interconnects and Reliability
- Electrostatic Discharge in Electronics
NHanced Semiconductors (United States)
2018-2024
North Carolina State University
2021
Tezzaron Semiconductor (United States)
2006-2017
Three-dimensional integrated circuits (3-D ICs) offer significant improvements over two-dimensional circuits, and promise a solution to the severe problems that are being, will be, encountered as monolithic process geometries reduced below 65 nm. Several methods associated with fabrication of 3-D ICs discussed in this paper, techniques developed by Tezzaron Semiconductor Corp., described detail. Four successful described, along anticipated benefits applying design future system-on-chip (SoC) devices.
The power target for exascale supercomputing is 20MW, with about 30% budgeted the memory subsystem. Commodity DRAMs will not satisfy this requirement. Additionally, large number of chips (>10M) required result in crippling failure rates. Although specialized DRAM memories have been reorganized to reduce through 3D-stacking or row buffer resizing, their implications on fault tolerance considered. We show that addressing reliability and energy a co-optimization problem involving tradeoffs...
This paper presents the first experimental demonstration of an energy-efficient electronic-photonic co-designed transceiver circuit heterogeneously 3D co-integrated with high-density, low-parasitic Direct Bond Interconnect (DBI <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> ) featuring 32-channel microdisk modulator/filter based optical transceivers for Wavelength Division Multiplexing (WDM) scheme. The silicon photonic chip is...
The vertically integrated photon imaging chip (VIPIC1) pixel detector is a stack consisting of 500-μm-thick silicon sensor, two-tier 34-μm-thick circuit, and host printed circuit board (PCB). tiers were bonded using the direct bonding technology with copper, each tier features 1-μm-diameter throughsilicon vias that used for connections to sensor on one side, PCB other side. 80-μm-pixel-pitch was nickel circuit. mounted Sn-Pb balls placed 320-μm pitch, yielding an entirely wire-bond-less...
The trend of increasing digital system performance by downscaling the device size poses daunting challenges in design due to increased power density, higher I/O count, interconnect bandwidth, and timing closure requirements. Silicon carrier with Through Vias (TSVs) or TSI technology is identified as a packaging level solution overcome all those challenges. In this paper we describe key electrical elements typical discuss their impact on overall performance. We also integrity analysis for its...
Compound semiconductor heterogeneous integration with silicon electronics offers new design opportunities for high performance microsystems. The indium phosphide (InP) material system is an attractive candidate of both electronic and optoelectronic devices. For RF mixed-signal integrated circuit (IC) applications, InP transistors offer the highest reported figures-of-merit, low transistor noise figure power density. We report on techniques performed at wafer-scale using hybrid bonding...
We describe a design and fabrication experiment that has been performed to investigate methodology for assessing the security of application specific integrated circuits (ASICs) fabricated in split-manufacturing process based on 3-D circuit (3DIC) technologies. The purpose this is protect critical IP from reverse engineering if an adversary obtains either wafers or their GDS. A number 3DIC-based alternatives were evaluated, one selected experiment. Several designs, trivial complex, used...
3D integrated circuit (3D-IC) technology gained acceptance due to the ability achieve extremely high level of integration, where hundreds ICs are stacked vertically. Such integration can result in local power dissipation more than 50 kW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This will lead instant evaporation IC, unless an effective cooling technique is employed. Liquid may be one most techniques for this task. To...
Driven by the internet bandwidth ever increasing demand, modern logic integrated circuits (IC) need to cope for memory (DRAM) data throughput above Terabit per seconds (Tbps) range [1]. Such DRAM interface is affected wall bottlenecks like: operating at much higher and lower latency than individual modules, with limited pin count capability organic packaging solutions leading system architecture using serialization techniques (at expense of power dissipation additional circuit latency)....
We present the first experimental demonstration of an electronic-photonic co-designed transceiver circuit heterogeneously 3D co-integrated with high-density, low-parasitic Direct Bond Interconnect (DBI ® ) featuring full SerDes that achieves -20.3dBm OMA sensitivity and 691fJ/bit link energy efficiency.
This letter presents a 25-Gb/s 3D-integrated optical receiver, which consists of an electronic integrated circuit (EIC) die fabricated in 12-nm FinFET technology and photonic (PIC) AIM Photonics' technology. EIC is flip-chip bonded to PIC through direct bond interconnect (DBI), allowing for significantly reduced parasitic. Except input-referred noise thanks improvements packaging, variable bandwidth transimpedance amplifier (TIA) with multistage feedback utilized further reduction front-end...
Tezzaron is continuing to push the level of 3D integration. The latest results a new 1-4Gb DRAM will be presented along with plans (and possibly some results) further integration other host logic devices. Additionally, from several recent integrations reviewed.
Wirebonds, although proven for space application and perceived necessary hybrid sensors like CdZnTe (CZT) detectors, introduce assembly complexity undesirable gaps between detector units. Thus, they pose a serious challenge in building low cost large area detector. We are developing Through-Silicon Vias (TSVs) to make all connections (both power data) through ASICs, which will eliminate wirebonds enable simple direct flip-chip bonding the ASIC substrate electronics layer. TSVs also more...
An optical transceiver architecture based on 12nm FinFET front-end circuits that are co-designed with silicon photonic microdisk modulators and drop filters achieves sub-500fJ/b operation at 18Gb/s. The transmitter utilizes a low-power quarter-rate architecture, while the receiver employs variable-bandwidth transimpedance amplifier for improved sensitivity.
In this paper, we describe the developments over past several years in field of 3D integrated circuits. integration offers far greater improvements than traditional semiconductor scaling can provide today. Considered part "More Than Moore" category technology, addition to increasing circuit and system density, circuits blend a wide range materials technologies into signal polylithic device acting as if these disparate items were truly fabricated together on single wafer. improvement power,...
This publication will cover Tezzaron's latest advancements in 2.5D and 3D technology including new wafer to integration of InP GaAs with CMOS devices work bonded die assembly sub 25um pitch. A manufacturing perspective the evolving customer requirements unique challenges testing these highly complex be discussed.
This paper presents an energy-efficient electronic-photonic co-designed transceiver heterogeneously 3D-integrated with high-density, low-parasitic direct bond interconnect (DBI <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> ) featuring 32-channel silicon photonic microdisk modulator/filter based optical transceivers in 12nm FinFET for wavelength division multiplexing (WDM). The transmitter has $1.2\mathrm{V}_{ppd}$ electrical modulation...
We present the first experimental demonstration of an electronic-photonic co-designed transceiver circuit heterogeneously 3D co-integrated with high-density, low-parasitic Direct Bond Interconnect (DBI <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> ) featuring full SerDes that achieves -20.3dBm OMA sensitivity and 691fJ/bit link energy efficiency.
It is widely agreed that memory the low hanging fruit of 2.5/3D integration. demonstrates advantages bringing togther semiconductor processees and technologies are difficult to cost effectively combine in an SOC. The presentation will describe latest efforts large memories with logic elements using interposers as well a more full 3D stacking approach. Discussion devices recently made those progress include results lessons learned.