This paper presents a technique that simulates load and generation changes outages of transmission lines transformers. The modification power injected into the system buses, which would simulate outage element, is calculated using sensitivity matrix basic state. real reactive flowing in elements voltages at all buses are then computed. proposed has been applied to Saskatchewan Power Corporation andto combined SPC Manitoba Hydro systems. flows bus calculatedby compared with those obtained...

Biometric security is a growing trend, as it supports the authentication of persons using confidential biometric data. Most transmitted data in multimedia systems are susceptible to attacks, which affect these systems. provide sufficient protection and privacy for users. The recently-introduced cancellable recognition have not been investigated presence different types attacks. In addition, they studied on large datasets. Another point that deserves consideration hardware implementation This...

The power consumption of wireline circuits has become increasingly more critical as the pin count and data rate rise. This paper describes a scaling methodology new half-rate speculative architecture for decision-feedback equalizers (DFEs) to relax speed-power trade-offs. Designed in 90-nm CMOS technology, 20-Gb/s prototype consisting linear equalizer one-tap DFE compensates loss an 18-in FR4 trace while drawing 40 mW from 1-V supply.

Incremental Delta-Sigma (I-DS) analog-to-digital converters (ADCs) are one of the best candidates for integrated sensor interface systems when it comes to high resolution and power efficiency. Advanced architectures such as Multistage noise shaping (MASH) or extended counting (EC) I-DS ADCs can be used achieve a fast conversion times avoid stability issues. Different have been proposed in state art (SoA), but there exists no extensive quantitative qualitative comparison between them. This...

<title>Abstract</title> <bold>Background: </bold>Hepatocellular carcinoma (HCC) is the sixth prevailing cancer globally and second greatest reason for cancer-linked deaths in males, surpassed only by lung cancer. A significant number of HCC cases experiencing advanced stages are due to frequent absence or inconspicuousness early symptoms. Consequently, discovering reliable diagnostic indicators innovative treatment targets essential improve survival overall outcomes patients. Herein, we...

The use of biometrics in security applications may be vulnerable to several challenges hacking. Thus, the emergence cancellable becomes a suitable solution this problem. This paper presents one-way biometric transform that depends on 3D chaotic maps for face and fingerprint encryption. It aims avoid cloning original allow templates used by each user different variable. permutations achieved with guarantee high templates, especially implementation encryption algorithm. In addition, hardware...

Low-power circuits often employ dynamic voltage scaling and energy harvesting. Such need a power management unit that can convert the source to wide range of target voltages with high efficiency. Targeting such unit, this paper presents reconfigurable architecture switched capacitor (SC) converter. It introduces design optimization methodology determine trade-off among parameters meet goal. The proposed converter employs topology four capacitors. provides 11 conversion ratios: 6 stepdown 5...

A charge pump circuit to minimize current mismatch and variation over a wide voltage compliance range is proposed. feedback loop used cancel both deterministic random mismatches between charging discharging PLL reference spurs static phase offset. compensation avoid bandwidth instability. The can operate at low supply voltage. power overhead due added circuitry 3.36% making it suitable for low-power low-voltage applications. proposed current-steering achieves lower than 0.44% the output from...

A linear equalizer with 9dB of boost and a 1-tap speculative half-rate DFE compensate for 24dB channel loss at 10GHz, generating an output BER less than 1012 eye opening 0.32UI. The circuit consumes 40mW from 1V supply 20Gb/s.

A novel sizing methodology for Dickson charge pumps with pure capacitive loads is presented. The based on dynamic analysis to minimize the rise time of pump up 25% under a given circuit area. validated through implementation six-stage pump-based driver in 180-nm standard low-voltage CMOS technology. used excitation ultrasonic transducers 34 V at resonance frequency 220 KHz. only 512 nS achieved. consumes 10.6 mA drawn from 5-V supply pumping 50 MHz and occupies an area 0.2 mm <sup...

This paper presents a 4-bit 20-GSps time-interleaved flash ADC for an ADC-based high-speed serial-link equalizer. The is designed and simulated in 65-nm CMOS technology. It dissipates 15.5 mW from 1-V supply while operating at 20 GSps. Low power consumption achieved by utilizing charge-steering concept, sharing single reference ladder across all the four interleaved branches, merging dynamic latch into pre-amplifier of comparator. Results show that sinusoidal input frequency 9.84 GHz with...

This paper presents an ultra low-power high-speed dynamic comparator. The proposed comparator is designed and simulated in a 65-nm CMOS technology. It dissipates 7 μW, 21.1 μW from 0.9-V supply while operating at 1 GHz, 3 GHz sampling clock respectively. Proposed circuit can work up to 14 GHz. Ultra low power consumption achieved by utilizing charge-steering concept proper sizing. Monte Carlo simulations show that the input referred offset contribution of internal devices negligible compared...

This paper presents a new differential power oscillator design based on class-E amplifier. The designs use high enhancement-GaN HEMT (e-GaN) for its fast switching time, low ON resistance and wide energy band gap properties. target application is far field wireless transfer charging applications. initial guess parameters follows the well known Sokal approach then LTSpice simulator used to finalize design. simulated output of 60 W at 433 MHz ISM with DC-to-RF conversion efficiency. Effect...

This paper presents the design of a low-power, 9-bit, two-step time-to-digital converter (TDC) in 65 nm CMOS. Instead using an array time amplifiers (TAs) to amplify residue, proposed TDC reduces power and area consumptions by only one TA. The designed achieves resolution 1.2 ps with conversion range 0.614 ns while consuming 0.602 mW at 10 MHz 8.299 150 MHz. achieved figure-of-merit (FoM) is 0.108 pJ/conversion frequency

The demand for low‐power equalisation at high data rates in serial‐link receivers has prioritised the issue of power consumption. This also involved phase‐locked loop (PLL) and clock recovery (CDR) circuits. propelled efforts to further optimise PLLs CDRs building blocks pursue solutions. A charge‐based phase interpolator (PI) is presented. It employs charge‐steering circuits order reduce typically consumed by its current‐based counterpart. Implemented 65‐nm CMOS technology, a 6‐bit PI...

A 4-channel 4-bit flash analog-to-digital converter is presented with 10Gbps sampling speed and a figure-of-merit of 182 fJ/conversion-step. It uses conventional clocking scheme, along modified sample-and-hold comparator chain circuits that reduce the overall ADC power consumption, enhances both resolution accuracy without need for any digital calibration. The designed using 65-nm CMOS technology tested input signals up to 5 GHz ENOB 3.7 bits. reported DNL INL are 0.42 LSB. channels...

It is widely accepted that the Epstein-Barr virus etiologically associated with development of nasopharyngeal carcinoma. The human papillomavirus also inverted papilloma. We used polymerase chain reaction technique to detect both viruses in types tumors. Flow cytometry was study DNA pattern and proliferative behavior tumors relation viruses. EBV detected 13/20 (65%) NPC specimens, none IP (n = 10) or control specimens 10). This indicates contribution as an etiologic factor NPC. Five cases...