This paper describes the issues and tradeoffs in design monolithic implementation of direct-conversion receivers proposes circuit techniques that can alleviate drawbacks this architecture. Following a brief study heterodyne image-reject topologies, architecture is introduced effects such as dc offset, I/Q mismatch, even-order distortion, flicker noise, oscillator leakage are analyzed. Related for amplification mixing, quadrature phase calibration, baseband processing also described.

Injection locking characteristics of oscillators are derived and a graphical analysis is presented that describes injection pulling in time frequency domains. An identity obtained from phase envelope equations used to express the requisite oscillator nonlinearity interpret noise reduction. The behavior phase-locked under also formulated.

This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis linear oscillatory system leads to shaping function and new definition Q. A model ring oscillators is used calculate their noise, three phenomena, namely, additive high-frequency multiplicative low-frequency are identified formulated. Based on the same concepts, relaxation oscillator also analyzed. Issues techniques related simulation time domain described, prototypes fabricated 0.5-/spl...

Precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described. Following a review conventional offset cancellation techniques, circuit designs achieving 12-b resolution both BiCMOS and CMOS 5-V technologies presented. The comparator consists preamplifier followed by two regenerative achieves an 200 mu V at 10-MHz clock rate while dissipating 1.7 mW. In is single-stage subsequent latch to achieve...

The StrongARM latch topology finds wide usage as a sense amplifier, comparator, or simply robust with high sensitivity. term “StrongARM” commemorates the use of this circuit in Digital Equipment Corporation’s microprocessor [1], but basic structure was originally introduced by Toshiba’s Kobayashi et al. [2]. has become popular for three reasons: 1) it consumes zero static power, 2) directly produces rail-to-rail outputs, and 3) its input-referred offset arises from primarily one...

Interleaving can relax the power-speed tradeoffs of analog-to-digital converters and reduce their metastability error rate while increasing input capacitance. This paper quantifies benefits derives an upper bound on performance by considering kT/C noise slewing requirements circuit driving system. A frequency-domain analysis interleaved is also presented that sheds light corruption mechanisms due to interchannel mismatches. background timing mismatch calibration technique proposed...

A modification of stacked spiral inductors increases the self-resonance frequency by 100% with no additional processing steps, yielding values 5 to 266 nH and frequencies 11.2 0.5 GHz. Closed-form expressions predicting less than 5% error have also been developed. Stacked transformers are introduced that achieve voltage gains 1.8 3 at multigigahertz frequencies. The structures fabricated in standard digital CMOS technologies four five metal layers.

A dual-band receiver employs the Weaver architecture with two tuned radio-frequency stages and a common intermediate-frequency stage to allow operation 900-MW 1.8-GHz standards while using only oscillators. Fabricated in digital 0.6-/spl mu/m CMOS technology, achieves an overall noise figure of 4.7 dB input third intercept point -8 dBm at 900 MHz, 4.9 -6 1.8 GHz. The voltage gain is 23 power dissipation 75 mW from 3-V supply.

The unlicensed band around 60 GHz can be utilized for wireless communications at data rates of several gigabits per second. This paper describes a receiver front-end that incorporates folded microstrip geometry to create resonance in common-gate LNA and active mixers. Realized 0.13-/spl mu/m CMOS technology, the provides voltage gain 28 dB with noise figure 12.5 while consuming 9 mW from 1.2-V supply.

A limiting amplifier incorporates active feedback, inductive peaking, and negative Miller capacitance to achieve a voltage gain of 50 dB, bandwidth 9.4 GHz, sensitivity 4.6 mV/sub pp/ for bit-error rate 10/sup -12/ while consuming 150 mW. driver employs T-coil peaking impedance conversion operation at 10 Gb/s delivering current 100 mA 25-/spl Omega/ lasers or swing 2 V/sub 50-/spl modulators with power dissipation 675 Fabricated in 0.18-μm CMOS technology, both prototypes operate 1.8-V supply.

This paper investigates the timing jitter of single-ended and differential CMOS ring oscillators due to supply substrate noise. We calculate resulting from noise, show that concept frequency modulation can be applied, derive relationships express different types in terms sensitivity oscillation or voltage. Using examples based on measured results, we thermal is typically negligible compared supply- substrate-induced high-speed digital systems. also discuss dependence transistor gate width,...

A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator a half-rate phase detector. The detector provides linear characteristic while retiming demultiplexing the with no systematic offset. Fabricated in 0.18-/spl mu/m CMOS technology area of 1.1/spl times/0.9 mm/sup 2/, exhibits RMS jitter 1 ps, peak-to-peak 14.5 ps recovered clock, bit-error rate 1.28/spl times/10/sup -6/, random input length 2/sup 23/-1. power dissipation is 72 mW...

An analysis of regenerative dividers predicts the required phase shift or selectivity for proper operation. A divider topology is introduced that employs resonance techniques by means on-chip spiral inductors to tune out device capacitances. Configured as two cascaded /spl divide/2 stages, circuit achieves a frequency range 2.3 GHz at 40 while consuming 31 mW from 2.5-V supply.

The design of analog and radio-frequency (RF) circuits in CMOS technology becomes increasingly more difficult as device modeling faces new challenges deep submicrometer processes emerging circuit applications. sophisticated set characteristics used to represent today's "digital" technologies often proves inadequate for RF design, mandating many additional measurements iterations arrive at an acceptable solution. This paper describes a characterization vehicles that can be employed quantify...

A large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, tolerance, generation. The results are validated by 1-Gb/s 10-Gb/s CMOS prototypes using an Alexander detector LC oscillator.

This paper describes the impact of gate resistance on cut-off frequency (f/sub T/), maximum oscillation max/), thermal noise, and time response wide MOS devices with deep submicron channel lengths. The value f/sub T/ is proven to be independent even for distributed structures. An exact relation max/ derived it shown that, predict max/, response, can divided by a factor 3 lumped into single resistor in series terminal.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML"...

Cognitive radios are expected to communicate across two or three frequency decades by continually sensing the spectrum and identifying available channels. This paper describes issues related design of wideband signal paths decades-wide synthesis carrier frequencies. A new CMOS low-noise amplifier topology for range 50 MHz 10 GHz is introduced that achieves a noise figure 2.9 5.7 dB with power dissipation 22 mW. Several multi-decade generation techniques proposed prototype presented exhibits...

Two equalizer filter topologies and a merged equalizer/CDR circuit are described that operate at 10 Gb/s in 0.13-mum CMOS technology. Using techniques such as reverse scaling, passive peaking networks, dual- triple-loop adaptation, the prototypes adapt to FR4 trace lengths up 24 inches. The retimes data with bit error rate of <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-13</sup> while consuming 133 mW from 1.6-V supply.