A5102009691- Radio Frequency Integrated Circuit Design
- Advancements in PLL and VCO Technologies
- Photonic and Optical Devices
- Microwave Engineering and Waveguides
- Semiconductor Lasers and Optical Devices
- Analog and Mixed-Signal Circuit Design
- Electromagnetic Compatibility and Noise Suppression
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor Quantum Structures and Devices
- Millimeter-Wave Propagation and Modeling
- Semiconductor materials and devices
- Optical Network Technologies
- Silicon and Solar Cell Technologies
- Advanced Wireless Communication Techniques
- Advanced MIMO Systems Optimization
- Spectroscopy and Laser Applications
- Advanced Frequency and Time Standards
- Electrostatic Discharge in Electronics
- Advanced Fiber Laser Technologies
- Ion-surface interactions and analysis
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Photonic Communication Systems
- 3D IC and TSV technologies
- Semiconductor materials and interfaces
- Advanced Electrical Measurement Techniques
Leibniz Institute for Neurobiology
2022-2024
Leibniz Institute for High Performance Microelectronics
2011-2022
Institut für Solartechnologien (Germany)
2003-2020
Leibniz Association
2011-2015
European University Viadrina
2015
University of California, Los Angeles
1999-2002
Institute of Semiconductor Physics
1997
University of Rostock
1992-1994
This paper investigates the timing jitter of single-ended and differential CMOS ring oscillators due to supply substrate noise. We calculate resulting from noise, show that concept frequency modulation can be applied, derive relationships express different types in terms sensitivity oscillation or voltage. Using examples based on measured results, we thermal is typically negligible compared supply- substrate-induced high-speed digital systems. also discuss dependence transistor gate width,...
An experimental SiGe HBT technology featuring fT/fmax/BVCEO = 505 GHz/720 GHz/1.6 V and a minimum CML ring oscillator gate delay of 1.34 ps is presented. The improved speed compared to our previous developments originates primarily from an optimized vertical profile, additional decrease the base emitter resistance which made possible by combining millisecond annealing with low-temperature backend, lateral device scaling.
A frequency synthesizer combining a relatively large tuning range (4.12-4.72 GHz) with low noise sensitivity is presented. stable fine-tuning loop combined an unstable coarse-tuning in parallel. As result, phase-locked (PLL) wide and moderate level of reference spurs obtained. By adding resistorless loop, the was increased by factor four no penalty terms phase noise, spurs, settling speed. Also, additional chip area power consumption are negligible. The CMOS PLL circuit fabricated 0.25-μm...
We present an analytical frequency-domain phase-noise model for fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> phase-locked loops (PLLs). The includes the noise of crystal reference, reference input buffer, voltage-controlled oscillator (VCO), loop filter, charge pump (CP) device noise, and sigma-delta modulator (SDM) including its effect on in-band phase noise. thermal CP turn-on time output current are found to be limiting...
The screened Coulomb Keldysh propagator is evaluated in the time-domain for ultra-short-pulse laser excitation of a semiconductor using nonequilibrium Green-function technique. buildup screening time interval during and shortly after pulse treated. A time-dependent plasmon pole approximation derived shown to give an excellent description dynamics resonant femtosecond pulse.
We present an integrated frequency synthesizer which is able to provide in-phase/quadrature phase signal over the bands 0.6-4.6 GHz, 5-7 10-14 and in-phase 20-28 GHz for software-defined radio applications. An voltage-controlled oscillator (VCO) with 34% tuning range a set of high-speed dividers are used accomplish all frequencies. To achieve wide while keeping low gain noise, VCO employs digitally controlled sub-bands. The measured PLL noise - 108 dBc/Hz, -121 -135 dBc/Hz at 1 MHz offset 24...
The standard deviation in a frequency modulated continuous wave radar distance measurement using charge pump phase-locked loop (PLL) is calculated analytically. phase noise of the PLL modeled as an Ornstein-Uhlenbeck process resulting Lorentzian spectrum. We calculate error function receiver bandwidth and target distance. Depending on estimation algorithm distance, rms due to increases by about 6-9 dB with doubling By contrast, white raises 12 far field doubling, making this contribution...
This paper presents the theoretical and experimental results on phase noise spectrum rms frequency error of a fractional-N phase-locked loop (PLL) under frequency-modulated continuous-wave (FMCW) chirp generation. The modulation is analytically calculated for second-order charge pump PLL with feedback divider ratio linearly changing over time. followed by an analysis steady-state output after settling achieved during A integrated ramp generator presented. Phase jitter measurements are...
An integrated PLL aimed at wireless transceivers in the unlicensed band from 59GHz to 64GHz is described. The was fabricated a SiGe:C BiCMOS technology with both f/sub T//f/sub max/=200GHz. measured lock range 53.3GHz 55.7GHz. It operates 3V supply except for first divide-by-two stage which requires 5V supply. Total power consumption 895mW.
We calculate the output power density spectrum for a simple voltage-controlled oscillator (VCO) circuit. The spectral of is composed term related to high-frequency fluctuations in feedback loop and low-frequency frequency control voltage. latter treated stochastically similar fashion inhomogeneous line broadening gas lasers due Doppler effect. This additional causes deviation from Lorentzian shape, that is, phase noise decay -6 dB per octave. specially pronounced at not-too-large offsets....
We describe a new approach to fully integrated CMOS LC-oscillators with very large tuning range. An experimental oscillator is tunable from 1.34 GHz 2.14 GHz. The standard deviation of the oscillation period due thermal device noise below 250 ppm. Potential applications include wideband RF systems and clock generation in microprocessors.
This paper presents a SiGe differential low-noise amplifier (LNA) for the V-band. The measured gain at 60 GHz is 18 dB, and input return loss below -15 dB. 3-dB bandwidth from 49 to 71 GHz. Measured simulated S-parameters agree well over whole range. LNA draws 30 mA 2.2 V supply. It facilitates design of fully integrated WLAN receiver in 57-64 band.
The effect of frequency modulation (FM) on the phase noise spectrum a charge pump phase-locked loop (PLL) for frequency-modulated continuous-wave (FMCW) radar is investigated. static error calculated as function ramp slope and basic PLL design parameters. under FM deduced from in steady state. Design guidelines integrated PLLs to be used FMCW are derived theoretical considerations experimental results literature.
This paper presents a wideband and low phase noise millimeter-wave (mm-wave) voltage-controlled oscillator (VCO) fabricated in 130 nm BiCMOS technology. The output signal can sweep from 29.6 to 35.5 GHz, which corresponds 18.1% tuning range. LC-tank of the VCO consists two coupled inductors binary weighted varactor bank. secondary inductor is terminated with switch realized heterojunction bipolar transistor (HBT). Depending on state, effective inductance LC-core be changed leads significant...
This paper presents a 60 GHz receiver front-end in SiGe:C BiCMOS technology. The conversion gain is 22 dB from to 5 without IF amplification. includes an LNA, mixer and 56 PLL. measured output 1-dB compression point -5dBm
A coupled set of equations for carrier distributions and stimulated emission in a semiconductor laser is presented, based on nonequilibrium Green's-function formulation. Carrier momentum-dependent dephasing caused by carrier-carrier scattering frequency-dependent optical gain are shown to govern the interplay between relaxation recombination. Ignoring interband Coulomb interaction, system distribution functions solved self-consistently single-mode short-cavity under steady-state operation...
In this report we propose a sensor architecture and corresponding read-out technique on silicon for the detection of dynamic capacitance change. This approach can be applied to rapid particle counting single sensing in fluidic system. The principle is based variation an interdigitated electrode (IDE) structure embedded oscillator circuit. scaling IDE results frequency modulation oscillator. A demodulator employed provide caused by self-calibrating at amplifier stage. due flow causing has...
This paper presents theoretical and experimental results on phase noise of differential CMOS oscillators. A simple analytical expression is derived verified by simulation which relates the including device excess factor to circuit parameters. In agreement with results, an 1.9-GHz oscillator yielded as low -100 dBc/Hz at 100-kHz offset a power consumption 12 mW. wide tuning range 250 MHz was obtained using PMOSFET's varicap only slight degradation phase-noise performance due varicap.
A fully integrated LC oscillator with a tuning range of 800 MHz is presented. combination capacitive and inductive has been used to produce the large low-gain control input. The phase noise at 1.9 GHz as low –120 dBc/Hz 500 kHz offset. Possible applications include integer-N PLLs level reference spurs.
Abstract. We present an analytical phase noise model for fractional-N phase-locked loops (PLL) with emphasis on integrated RF synthesizers in the GHz range. The of crystal reference, voltage-controlled oscillator (VCO), loop filter, charge pump, and sigma-delta modulator (SDM) is filtered by PLL operation. express rms error (jitter) terms VCO third-order filter parameters. In addition, we consider OFDM systems, where reduced digital signal processing after down-conversion to baseband....
A fully integrated voltage-controlled oscillator (VCO) with a 17% tuning range and low phase noise fabricated in 0.25 µm SiGe BiCMOS technology is presented. To achieve wide while keeping gain (KVCO), the VCO has 16 bands selectable by 4-bit digital control. Coarse achieved using MOSFET varactors manner, which reduces loss resonator. The measured −111 dBc/Hz at 1 MHz offset from 22 GHz carrier. This level believed to be lowest reported so far for an silicon-based 20–30 frequency band.
We present a single-chip fractional-N PLL for space applications. The design employs high-current charge pump with optimum output biasing and low-current extension of the tuning range. show that range does not increase phase noise reference spurs. is tunable from 17.5 GHz to 18.9 GHz, at 1 MHz offset below -110 dBc/Hz. Since loop bandwidth are almost independent frequency, robust against parameter variations process, voltage, temperature, ageing.
In this paper, a fractional-N phase-locked loop (PLL) with an integrated chirp generation circuit block for frequency-modulated continuous-wave (FMCW) radar systems is reported. The composed of push-push voltage controlled oscillator (VCO), feedback divider including pre-scaler and programmable stages, phase-frequency detector followed by current steering charge pump, sigma-delta modulator (SDM) 18-bit resolution, generator serial-peripheral-interface (SPI) programming the generator....
A frequency divider providing quadrature outputs up to 30GHz is presented. Rms phase error and rms clock jitter are discussed in the context of OFDM systems, where usual correction digital baseband processor included. measurement technique for static between in-phase signal proposed using an integrated single-sideband mixer conjunction with 1:256 divider. For a 20GHz I/Q output 0.16° obtained from these measurements. The core draws 35mA 3.3 V supply occupies 0.2 mm2 chip area, including...
An integrated frequency synthesizer for 28.733.7 GHz is presented. This wide tuning range achieved at low phase noise by combining capacitive and inductor switching in the voltage-controlled oscillator (VCO). The lends itself to realization of transceiver frontends when using a sliding-IF architecture, both 28 38 band. It occupies chip area 5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including bondpads draws 171 mA from 2.5 V...