A5086433249- Particle accelerators and beam dynamics
- Particle Accelerators and Free-Electron Lasers
- Radio Frequency Integrated Circuit Design
- Gyrotron and Vacuum Electronics Research
- Advancements in PLL and VCO Technologies
- Microwave Engineering and Waveguides
- Advanced Power Amplifier Design
- Superconducting Materials and Applications
- Particle Detector Development and Performance
- Energy Harvesting in Wireless Networks
- Analog and Mixed-Signal Circuit Design
- Semiconductor materials and devices
- Advanced X-ray Imaging Techniques
- Pulsed Power Technology Applications
- Laser-Plasma Interactions and Diagnostics
- Tribology and Wear Analysis
- Antenna Design and Optimization
- Electrostatic Discharge in Electronics
- Wireless Power Transfer Systems
- GaN-based semiconductor devices and materials
- 3D IC and TSV technologies
- Wireless Communication Networks Research
- Photocathodes and Microchannel Plates
- Electromagnetic Compatibility and Noise Suppression
- Error Correcting Code Techniques
Broadcom (United States)
2007-2023
Imperial College London
2023
MRC Centre for Environment and Health
2023
Broadcom (Israel)
2008-2012
Massachusetts Institute of Technology
1997-2006
Bates College
2000-2006
Advanced Micro Devices (United States)
2004-2005
University of California, Los Angeles
2001-2003
Budker Institute of Nuclear Physics
2002
Diversified Technologies (United States)
2002
A modification of stacked spiral inductors increases the self-resonance frequency by 100% with no additional processing steps, yielding values 5 to 266 nH and frequencies 11.2 0.5 GHz. Closed-form expressions predicting less than 5% error have also been developed. Stacked transformers are introduced that achieve voltage gains 1.8 3 at multigigahertz frequencies. The structures fabricated in standard digital CMOS technologies four five metal layers.
A 2.4-GHz CMOS receiver/transmitter incorporates circuit stacking and noninvasive baseband filtering to achieve a high sensitivity with low power dissipation. Using single 1.6-GHz local oscillator, the transceiver employs two upconversion downconversion stages while providing on-chip image rejection filtering. Realized in 0.25-μm digital technology, receiver exhibits noise figure of 6 dB consumes 17.5 mW from 2.5-V supply, transmitter delivers an output 0 dBm consumption 16 mW.
802.11n is the latest offering from IEEE standard committee tasked with enabling and enhancing WLAN systems. This utilizes several techniques to offer a much larger rate versus range than legacy A single-chip multiband direct-conversion CMOS MIMO transceiver (2times2) targeted for applications presented. capable of satisfying requirements draft 802.1 In achieves PHY rates > 270 Mb/s. The receivers transmitters achieve an EVM better -41 dB (0.9%) -40 (1.0%) operating in g modes, respectively....
A fully integrated SoC compliant with 802.11 a/b/g/ssn, BT, and FM standards is presented. Shared blocks include LNA, PA, crystal, bandgap, RCAL. The WLAN, receivers achieve sensitivities better than -76 dBm (54 Mb/s/2.4 Ghz), -91 dBm, 1 uV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> , respectively. WLAN BT transmitters linear output powers of 21 10
A low-power, multimode polar transmitter based on a two-point injection PLL with linearized VCO is implemented in 65-nm CMOS technology. wideband feedback loop, nested inside the negligible area and power consumption overhead, linearizes accurately controls tuning characteristic of VCO, which key requirement when directly modulating oscillator. Differential delay between AM-PM paths predictable self-calibrated. In WCDMA mode, achieves 42/-58-dBc ACLR at 5/10-MHz offsets, -159-dBc/Hz receive...
This paper presents a single-chip dual-band CMOS direct-conversion transceiver fully compliant with the IEEE 802.11a/b/g standards. Operating in frequency ranges of 2.412-2.484 GHz and 4.92-5.805 (including Japanese band), fractional-N PLL based synthesizer achieves an integrated (10 kHz-10 MHz) phase noise 0.54/spl deg//1.1/spl deg/ for 2/5-GHz band. The transmitter error vector magnitude (EVM) is -36/-33 dB output power level higher than -3/-5dBm receiver sensitivity -75/-74 dBm band 64QAM...
A quad-band 2.5G SoC integrating all the RF, DSP, ARM, audio and other baseband processing functions into a single 65 nm CMOS die is described. The paper focuses on radio portion mostly, addresses challenges of realizing complete GSM/EDGE with RF integrated along rest digital circuitry. Several circuit level as well architectural techniques are presented to realize very low-cost low-power while meeting stringent cellular requirements wide margin. draws battery current 49 mA in receiver-mode,...
London has outperformed smaller towns and rural areas in terms of life expectancy increase. Our aim was to investigate change at very-small-area level, its relationship with house prices their change. We performed a hyper-resolution spatiotemporal analysis from 2002 2019 for 4835 Lower-layer Super Output Areas (LSOAs). used population death counts Bayesian hierarchical model estimate age- sex-specific rates each LSOA, converted birth using table methods. data the Land Registry via real...
The generation of brilliant, stable, and broadband coherent synchrotron radiation (CSR) in electron storage rings depends strongly on ring rf system properties such as frequency gap voltage. We have observed intense at frequencies approaching the THz regime produced by MIT-Bates South Hall Ring, which employs a high-frequency $S$-band system. measured CSR spectral intensity enhancement with 2 mA stored current was up to 10 000 times above background for wave numbers near $3\text{ }\text{...
This radio integrates all the receive and transmit functions required to support a quad-band GSM/GPRS/EDGE application into single CMOS chip. Compared published work, this transceiver is implemented in low-cost digital 0.13 mum CMOS, achieves superior performance, yet has up 2x lower power consumption, key requirement cellular applications.
A low-power 802.11abg SoC which achieves the best reported sensitivity as well lowest power consumption and utilizes an extensive array of auto calibrations is reported. This a two-antenna receiver to build single weight combiner (SWC) system. new signal-path Cartesian phase generation combination technique proposed that shifts RF signal in 22.5deg steps. 3 dB improvement received SNR achieved comparison path receiver. The radio AFE occupy 10 mm <sup...
So far all mainstream transmitters for WCDMA are of the direct upconversion type. This architecture is versatile but requires calibration imbalance in its quadrature branches and DC offset at inputs, it vulnerable to mixer noise. We believe consumes more power chip area than warranted, propose polar transmitter as an alternative. Although has been widely discussed ideal EDGE, yet make significant inroads there, let alone into wideband CDMA. will describe new circuits that enable a compact,...
In cellular applications, open-loop small-signal polar transmitters offer several advantages such as low power consumption and small silicon area. However, due to their complexity, circuit imperfections can severely affect performance, potentially rendering them impractical meet the challenging transmitter requirements. this paper a detailed analysis of direct-modulated for GSM/EDGE/WCMA applications are provided followed by some case studies. Several key non-idealities will be discussed...
A low-power single-chip Bluetooth EDR device is realized using a configurable transformer-based RF front-end, low-IF receiver and direct-conversion transmitter architecture. It implemented in 0.13mum CMOS process occupies 11.8mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Sensitivity for 1, 2 3Mb/s rates -88, -90, -84dBm differential EVM 5.5% rms.
A single-chip multi-band direct-conversion CMOS MIMO transceiver (2 times 2) targeted for WLAN applications is presented. This capable of satisfying the requirements Enhanced Wireless Consortium and achieves PHY rates >270Mb/s. The receivers transmitters achieve an EVM better than -41 dB (0.9%) -40dB (1.0%) operating in legacy g a modes, respectively. From 1.8V supply with both cores operating, chip draws 275mA RX mode 280mA TX mode.
A modification of stacked spiral inductors increases the self-resonance frequency by 100% with no additional processing steps, yielding values 5 nH to 266 and frequencies 11.2 GHz 0.5 GHz. Closed-form expressions predicting less than 5% error have also been developed. 1-to-2 transformer consisting 3 spirals achieves a voltage gain 1.8 at 2.5 The structures fabricated in standard CMOS technologies four five metal layers.
A multi-mode WPAN transceiver implemented in an SoC is presented. Fabricated 40-nm CMOS, the chip supports IEEE 802.15.4 and all modes of Bluetooth. Consuming 7.8 mW from a 1.2-V supply, receiver has sensitivity -104, -98, -95/-94/-88 dBm 802.15.4, BLE Bluetooth BDR/EDR2/EDR3, respectively. The transmitter power consumption 10 to deliver 0 output constant envelope mode 14.5 BT EDR.
The proliferation of 2.4 GHz wireless standards such as Bluetooth and IEEE802.11b makes it desirable to realize low-power, compact transceivers capable interoperability between frequency-hopping direct-sequence systems. While requirements for receiver sensitivity phase noise transmitter linearity are relatively relaxed, those much more stringent. This paper describes a transceiver targeting both standards. frequency planning the design all building blocks achieve low power dissipation...
This paper presents a single chip dual-band transceiver, fully compliant with the IEEE 802.11 a/b/g standards. Operating in frequency ranges of 2.412-2.484 GHz and 4.92-5.805 (including Japanese band), fractional-N PLL based synthesizer achieves an integrated (10 kHz-10 MHz) phase noise 0.54/spl deg//1.1/spl deg/ for 2/5-GHz band. The transmitter error-vector-magnitude (EVM) is -36/-33 dB output power level higher than -3/-5 dBm receiver sensitivity better -70 band 64QAM at 54 Mb/s.
The MIT-Bates Linear Accelerator Center is in the process of constructing an electron storage ring. 190-m ring will be used for internal target experiments with stored beams. It also as a pulse stretcher to provide external beams high duty factors. present design incorporates low beta region /sub x/ 1 m and 4.5 m-space between quadrupoles at location. contain up 80 mA using two turn injection. Extraction one-half integer resonance produce 50 mu A factor over 80%. Injection occur kHz. Design...
A quad-band 2.5G SoC integrates all the RF, DSP, ARM, audio and other baseband processing functions into a single 65nm CMOS die. The radio draws battery current of 49mA in RX-mode, 86mA GMSK TX-mode. low-IF receiver achieves sensitivity -110dBm at antenna, corresponding to noise figure 2.4dB device input. 8PSK ±400kHz modulation mask is -64.1/62.7dBc for high/low bands, with an RMS EVM 2.45/1.95%.
A fourth-order filter incorporates a method of suppressing interferers without filtering the desired signal, relaxing trade-offs between noise, linearity, and power dissipation. Designed for baseband 2.4 GHz receiver fabricated in 0.25 /spl mu/m CMOS technology, exhibits an input-referred noise 17 nV//spl radic/(Hz) while dissipating 2 mW from 2.5 V supply achieves figure 6 dB with consumption 17.5 mW.