A5008825029- Social and Educational Sciences
- Education, Healthcare and Sociology Research
- Research in Social Sciences
- Cultural Industries and Urban Development
- European and International Law Studies
- Analog and Mixed-Signal Circuit Design
- Knowledge Management and Sharing
- Team Dynamics and Performance
- Higher Education Governance and Development
- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- Public Relations and Crisis Communication
- Regional Development and Policy
- Low-power high-performance VLSI design
- Media Studies and Communication
- Higher Education Learning Practices
- Social Policy and Reform Studies
- Information Systems and Technology Applications
- Historical and Archaeological Studies
- Advanced Power Amplifier Design
- Innovation, Technology, and Society
- Management and Organizational Practices
- Marketing and Advertising Strategies
- Rural development and sustainability
- Business Strategy and Innovation
University of South-Eastern Norway
2022
Roskilde University
2008-2019
Copenhagen Business School
2011-2016
Broadcom (United States)
2007-2015
Broadcom (Israel)
2008-2014
University of Wuppertal
2014
John Brown University
2014
Cadence Design Systems (United States)
2014
California Institute of Technology
2014
Chalmers University of Technology
2014
Although /spl Delta//spl Sigma/ modulators are widely used for low to moderate rate analog-to-digital conversion, the time oversampling requirement has discouraged their application higher converters. This paper presents an architecture wherein multiple combined so that neither nor interlacing necessary. Instead, system achieves effect of from multiplicity modulators. For a containing M P/sup th/-order modulators, approximately P bits accuracy gained every doubling M. A major benefit is it...
This study investigates the influence of Green Supply Chain Initiatives (GSCI) on Corporate Performance (CP), emphasizing mediating role Operational Efficiency (OE). Using Partial Least Squares Structural Equation Modeling (PLS-SEM) through SmartPLS, research analyzes survey data collected from SESINDO organizations. GSCI, encompassing practices such as green procurement, eco-design, and waste management, are examined for their impact financial, operational, environmental performance. The...
Conventional delta-sigma analog-to-digital converters (/spl Delta//spl Sigma/ADC's) are widely used in low-bandwidth applications such as high-fidelity audio processing because they offer high-precision conversion yet amenable to implementation using fine-line VLSI processes optimized for digital circuitry. However, their oversampling requirement so far has prevented widespread application higher bandwidth video processing. This paper extends a recently developed ADC architecture called the...
This paper presents and analyzes a new dynamic element matching technique for low-harmonic distortion digital-to-analog conversion. The benefit of this over the prior art is significantly reduced hardware complexity with no reduction in performance. It particularly appropriate applications such as direct digital synthesis (DDS) wireless communications systems, where low harmonic are essential.
Digital entrants have changed the competitive landscape for advertisers and media. Over past decade, media agencies grown more rapidly than market as a whole, securing larger share of value generated in advertising industry. We develop process model describing how these altered their business models over decade. discuss three separate stages this innovation process, labelled (BMI) awareness, exploration, exploitation. find document different building blocks are focal point each stage BMI...
A quad-band 2.5G SoC integrating all the RF, DSP, ARM, audio and other baseband processing functions into a single 65 nm CMOS die is described. The paper focuses on radio portion mostly, addresses challenges of realizing complete GSM/EDGE with RF integrated along rest digital circuitry. Several circuit level as well architectural techniques are presented to realize very low-cost low-power while meeting stringent cellular requirements wide margin. draws battery current 49 mA in receiver-mode,...
This paper presents a second-order /spl Delta//spl Sigma/ modulator for audio-band analog-to-digital conversion implemented in 3.3-V, 0.5-/spl mu/m, single-poly CMOS process using metal-metal capacitors that achieves 98-dB peak signal-to-noise-and-distortion ratio and 105-dB spurious-free dynamic range. The design uses low-complexity, first-order mismatch shaping 33-level digital-to-analog converter flash with digital common-mode rejection element matching of comparator offsets. These...
This radio integrates all the receive and transmit functions required to support a quad-band GSM/GPRS/EDGE application into single CMOS chip. Compared published work, this transceiver is implemented in low-cost digital 0.13 mum CMOS, achieves superior performance, yet has up 2x lower power consumption, key requirement cellular applications.
In cellular applications, open-loop small-signal polar transmitters offer several advantages such as low power consumption and small silicon area. However, due to their complexity, circuit imperfections can severely affect performance, potentially rendering them impractical meet the challenging transmitter requirements. this paper a detailed analysis of direct-modulated for GSM/EDGE/WCMA applications are provided followed by some case studies. Several key non-idealities will be discussed...
A low-power single-chip Bluetooth EDR device is realized using a configurable transformer-based RF front-end, low-IF receiver and direct-conversion transmitter architecture. It implemented in 0.13mum CMOS process occupies 11.8mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Sensitivity for 1, 2 3Mb/s rates -88, -90, -84dBm differential EVM 5.5% rms.
In order to achieve noise figure smaller than 1dB, the GNSS receivers require external LNA, which adds area, cost and current consumption. A 28nm CMOS sub-1dB NF 9mW receiver is presented, requiring no components. This work takes advantage of symmetry in performance between NMOS PMOS at node demonstrates that low possible on advanced power levels, with proper design on-chip matching
This paper presents a robust, low complexity clock distribution technique applicable to both printed circuit boards and integrated circuits. The exploits the natural tendency of certain oscillators lock in frequency nearly phase when coupled together. Experimental theoretical results are presented that indicate has potential dramatically reduce skew digital A architecture using is proposed.
Partial randomization dynamic element matching (DEM) was recently introduced as a promising DEM technique for low harmonic distortion digital-to-analog conversion. The is well suited to applications such direct digital synthesis in wireless communication systems which hardware complexity essential addition distortion. Previously reported simulation results demonstrate that partial greatly attenuates resulting from static errors the analog output levels of DAC, while offering considerable...
A quad-band 2.5G SoC integrates all the RF, DSP, ARM, audio and other baseband processing functions into a single 65nm CMOS die. The radio draws battery current of 49mA in RX-mode, 86mA GMSK TX-mode. low-IF receiver achieves sensitivity -110dBm at antenna, corresponding to noise figure 2.4dB device input. 8PSK ±400kHz modulation mask is -64.1/62.7dBc for high/low bands, with an RMS EVM 2.45/1.95%.
Although mismatch-shaping multi-bit DACs offer many advantages over single-bit in delta-sigma data converters, most of the presently known DAC architectures involve a large amount digital processing. This paper presents structures that implement previously published tree-structured algorithms yet significant reductions
A dynamic element matching (DEM) technique to mitigate the distortion caused by comparator offsets in flash ADC of a /spl Delta//spl Sigma/ modulator is presented. Measurement results for high-performance IC using offset DEM are shown demonstrate significant reduction offset-related spurious tones provides. Analysis and simulation with periodic input uniform dither presented give insight into its operation quantify spur attenuation it
This paper presents a second-order /spl Delta//spl Sigma/ modulator for audio-band A/D conversion implemented in 3.3 V, 0.5 mu/m, single-poly CMOS process that achieves 98 dB peak SINAD and over 100 SFDR. The design uses reduced-complexity, mismatch-shaping 33-level DAC flash ADC with digital common-mode rejection dynamic element matching of comparator offsets. These signal processing innovations, combined established circuit techniques, enable state the art performance optimized circuits....