A5061267008- Analog and Mixed-Signal Circuit Design
- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- Low-power high-performance VLSI design
- CCD and CMOS Imaging Sensors
- Advancements in Semiconductor Devices and Circuit Design
- Electromagnetic Compatibility and Noise Suppression
- Semiconductor Lasers and Optical Devices
- EEG and Brain-Computer Interfaces
- Photonic and Optical Devices
- Neuroscience and Neural Engineering
- Numerical Methods and Algorithms
- Sensor Technology and Measurement Systems
- Digital Filter Design and Implementation
- Advanced Power Amplifier Design
- Advanced Electrical Measurement Techniques
- Advanced Memory and Neural Computing
- Parallel Computing and Optimization Techniques
- Advanced DC-DC Converters
- Microwave Engineering and Waveguides
- Neural dynamics and brain function
- VLSI and Analog Circuit Testing
- Embedded Systems Design Techniques
- Interconnection Networks and Systems
- Neural Networks and Applications
University of California, San Diego
2016-2025
UC San Diego Health System
2019
Qualcomm (United Kingdom)
2014
University of California System
2013
University of California, Los Angeles
2003-2010
Institute of Microelectronics
2008
Irvine University
1993-2002
University of California, Irvine
1995-2002
California Institute of Technology
1989
Electrophysiological devices are critical for mapping eloquent and diseased brain regions therapeutic neuromodulation in clinical settings extensively used research brain-machine interfaces. However, the existing experimental often limited either spatial resolution or cortical coverage. Here, we developed scalable manufacturing processes with a dense electrical connection scheme to achieve reconfigurable thin-film, multithousand-channel neurophysiological recording grids using platinum...
A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, presented demonstrated as enabling components in wideband CMOS delta-sigma fractional-N phase-locked loop (PLL). The PLL has bandwidth 460 kHz is capable 1-Mb/s in- FSK modulation at center frequencies 2402 + k MHz for = 0, 1, 2, ..., 78. For each frequency, measured results indicate that the peak spot reduction achieved by 16 dB or better, minimum suppression...
Recently, various multibit noise-shaping digital-to-analog converters (DACs) have been proposed that use digital signal processing techniques to cause the DAC noise arising from analog component mismatches be spectrally shaped. Such DACs potential significantly increase present precision limits of /spl Delta//spl Sigma/ data by eliminating need for one-bit quantization in delta-sigma modulators. This paper extends practicality approach presenting a general architecture along with two...
A 1.8-V 15-bit 40-MSample/s CMOS pipelined analog-to-digital converter with 90-dB spurious-free dynamic range (SFDR) and 72-dB peak signal-to-noise ratio (SNR) over the full Nyquist band is presented. Its differential integral nonlinearities are 0.25 LSB 1.5 LSB, respectively, its power consumption 400 mW. This performance enabled by digital background calibration of internal digital-to-analog (DAC) noise interstage gain errors. The achieves improvements better than 12 dB in plus distortion...
This paper presents a reconfigurable continuous-time delta-sigma modulator for analog-to-digital conversion that consists mostly of digital circuitry. It is voltage-controlled ring oscillator based design with new background calibration and self-cancelling dither techniques applied to enhance performance. Unlike conventional modulators, it does not contain analog integrators, feedback DACs, comparators, or reference voltages, require low-jitter clock. Therefore, uses less area than...
An enhancement to a conventional integer-N phase-locked loop (PLL) is introduced, analyzed, and demonstrated experimentally significantly reduce voltage-controlled oscillator (VCO) phase noise. The enhancement, which involves periodically injection locking the VCO buffered version of reference, has effect widening PLL bandwidth reducing overall It in 3-V 6.8-mW CMOS reference with ring capable converting most popular crystal frequencies 96-MHz RF baseband clock for direct conversion...
This paper presents a pipelined ADC with two fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue amplifier gain error and nonlinearity DAC noise cancellation (DNC) capacitor mismatches. It is the first IC implementation of HDC, results demonstrate that HDC DNC together facilitate low-voltage operation enable reductions in power dissipation relative comparable conventional state-of-the-art ADCs. The achieves peak SNR 70 dB...
Pipelined analog-to-digital converters (ADCs) tend to be sensitive component mismatches in their internal digital-to-analog (DACs), The give rise error, referred as DAC noise, which is not attenuated or cancelled along the pipeline are other types of noise. This paper describes an all-digital technique that significantly mitigates this problem. continuously measures and cancels portion ADC error arising from noise during normal operation ADC, so no special calibration signal auto-calibration...
This paper describes a fractional-N PLL IC based on new digital quantizer that replaces the DeltaSigma modulator (DeltaSigmaM) used in conventional designs. In combination with charge pump offset technique and sampled loop filter enables state-of-the-art fractional spur performance without sacrificing BW.
A fast-settling adaptive calibration technique is presented that makes phase noise cancelling DeltaSigma fractional-N PLLs practical for the low reference frequencies commonly used in wireless communication systems. The demonstrated as an enabling component of a 2.4 GHz ISM band CMOS PLL IC with 730 kHz bandwidth, 12 MHz reference, and on-chip loop filter. In addition to technique, incorporates dynamic charge pump biasing reduce power dissipation. worst-case -101 dBc/Hz -124 at 100 3...
This paper demonstrates that spurious tones in the output of a fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> PLL can be reduced by replacing DeltaSigma modulator with new type digital quantizer and adding charge pump offset combined sampled loop filter. It describes underlying mechanisms tones, proposes techniques mitigate effects mechanisms, presents phase noise cancelling 2.4 GHz ISM-band CMOS techniques. The has 975 kHz...
This paper presents a second-generation mostly-digital background-calibrated oversampling ADC based on voltage- controlled ring oscillators (VCROs). Its performance is in line with the best ΔΣ modulator ADCs published to date, but it occupies much less circuit area, reconfigurable, and consists mainly of digital circuitry. Enhancements relative first-generation version include digitally open-loop <i xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This jump-start tutorial brief explains the principle that underlies all of published mismatch-scrambling and mismatch-shaping dynamic-element-matching (DEM) digital-to-analog converters (DACs). It apparent paradox how an all-digital algorithm can cause analog component mismatches to introduce spectrally shaped noise instead nonlinear distortion, even though has no knowledge actual mismatches. The concept is first explained in context a discrete-time three-level DEM DAC. results are then...
High-performance analog-to-digital converters, digital-to-analog and fractional-N frequency synthesizers based on delta-sigma (/spl utri//spl Sigma/) modulation - collectively referred to as /spl Sigma/ data converters have contributed significantly the high level of integration seen in recent commercial wireless handset transceivers. This paper presents a tutorial their uses implications with respect transceiver architectures.
Pipelined analog-to-digital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, amplifier tends be inversely related power consumption practice, so usually dominant consumers of high-resolution pipelined ADCs. This paper presents a background calibration technique that digitally measures and cancels ADC error arising from amplifiers. It allows use higher and, therefore, lower high-accuracy ADCs, thereby significantly...
Although /spl Delta//spl Sigma/ modulators are widely used for low to moderate rate analog-to-digital conversion, the time oversampling requirement has discouraged their application higher converters. This paper presents an architecture wherein multiple combined so that neither nor interlacing necessary. Instead, system achieves effect of from multiplicity modulators. For a containing M P/sup th/-order modulators, approximately P bits accuracy gained every doubling M. A major benefit is it...
Theoretical sufficient conditions are presented that ensure the quantization noise from every constituent digital delta-sigma (DeltaSigma) modulator in a multistage DeltaSigma is asymptotically white and uncorrelated with input. The also determine if spectral shape can be imparted to dither's contribution power density of modulator's output. A large class popular modulators satisfy identified tabulated for easy reference
An analysis of the quantization noise introduced by a widely-used class single-quantizer digital delta-sigma (DeltaSigma) modulators with low-level, 1-bit dither is presented. Necessary and sufficient conditions are derived that ensure, in an asymptotic sense, various ensemble statistical properties such as uniformity independence from input delayed versions itself. The also shown to be for single realization sequence possess these time-averaged sense. Several most commonly-used DeltaSigma satisfy
This paper demonstrates a high speed digital technique to produce binary (digital) signals that encode representative RF (with time varying envelope) as needed for wireless communications. Specifically, it shows IS-95 format CDMA can be generated with single bit data stream at 3.6 Gb/S. The uses band-pass delta-sigma modulation so the quantization noise is shaped out of frequency band interest. approach points way single-chip, DSP-based transmitters, used in conjunction switching mode power...
A gain error correction (GEC) technique is presented that continuously measures and digitally compensates for analogue errors present in each stage of a pipelined analogue-to-digital-converter (ADC). Simulations with without the GEC indicate results large improvement signal-to-noise-and-distortion (SINAD) spurious-free-dynamic-range (SFDR) converter.
This paper shows analytically and experimentally that properly-designed dynamic element matching (DEM) eliminates pulse shape, timing, amplitude errors arising from component mismatches as sources of nonlinear distortion in high-resolution DACs. A set sufficient conditions on the DEM encoder ensure this effect, a specific segmented satisfies are presented. Unlike most previously published encoders, new encoder's complexity does not grow exponentially with number bits DAC resolution, so it is...
Precision oscillators are ubiquitous in modern electronic systems, and their accuracy often limits the performance of such systems. Hence, a deep understanding how oscillator is quantified, simulated, measured, it affects system essential for designers. Unfortunately, necessary information spread thinly across published literature textbooks with widely varying notations some critical disconnects. This paper addresses this problem by presenting comprehensive one-stop explanation error...
Conventional delta-sigma analog-to-digital converters (/spl Delta//spl Sigma/ADC's) are widely used in low-bandwidth applications such as high-fidelity audio processing because they offer high-precision conversion yet amenable to implementation using fine-line VLSI processes optimized for digital circuitry. However, their oversampling requirement so far has prevented widespread application higher bandwidth video processing. This paper extends a recently developed ADC architecture called the...