A5036232001- Radio Frequency Integrated Circuit Design
- Advancements in PLL and VCO Technologies
- Advanced Power Amplifier Design
- Microwave Engineering and Waveguides
- Wireless Communication Networks Research
- Analog and Mixed-Signal Circuit Design
- Electromagnetic Compatibility and Noise Suppression
- Acoustic Wave Resonator Technologies
- Interconnection Networks and Systems
- Mitochondrial Function and Pathology
- Neurological disorders and treatments
- Electrostatic Discharge in Electronics
- Genetic Neurodegenerative Diseases
National Taiwan University Hospital
2024
Broadcom (United States)
2003-2015
Broadcom (Israel)
2005-2010
Carleton University
2006
Based on the physical understanding of noise mechanisms in active mixers, a cancellation technique to reduce flicker contribution switches Gilbert-type mixer is presented. For proof concept, prototype double-balanced 0.13 /spl mu/m CMOS fabricated. The circuit achieves corner almost an order magnitude lower than that standard implementation, without any penalty linearity, gain, or power consumption.
A quad-band 2.5G SoC integrating all the RF, DSP, ARM, audio and other baseband processing functions into a single 65 nm CMOS die is described. The paper focuses on radio portion mostly, addresses challenges of realizing complete GSM/EDGE with RF integrated along rest digital circuitry. Several circuit level as well architectural techniques are presented to realize very low-cost low-power while meeting stringent cellular requirements wide margin. draws battery current 49 mA in receiver-mode,...
A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built 0.18-/spl mu/m CMOS. All of the radio building blocks including power amplifier (PA), phase-locked loop (PLL) filter, and antenna switch, as well complete baseband physical layer medium access control (MAC) sections, have been into a single chip. The tuned to 2.4 GHz dissipates 165 mW receive mode 360 transmit from 1.8-V supply. receiver achieves typical noise figure 6 dB -88-dBm sensitivity at 11...
A fully integrated dual-mode CMOS transceiver tuned to 2.4 GHz consumes 65 mA in receive mode and 78 transmit from a 3-V supply. The radio includes all the building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), power amplifier, is intended for use 802.11b Bluetooth applications. receiver uses low-IF architecture higher level of integration lower consumption, while direct conversion. achieves typical sensitivity -88 dBm at 11 Mb/s 802.11b, -83 mode. minimum IIP3...
This radio integrates all the receive and transmit functions required to support a quad-band GSM/GPRS/EDGE application into single CMOS chip. Compared published work, this transceiver is implemented in low-cost digital 0.13 mum CMOS, achieves superior performance, yet has up 2x lower power consumption, key requirement cellular applications.
An IP2 calibration circuit to improve the 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order nonlinearity of mixers in zero or low-IF receivers is presented. The allows be optimized independently, and has negligible impact on receiver noise figure, area, power consumption. A prototype transceiver including circuitry 0.13μm CMOS fabricated. average IIP2 improvement 18dB measured
A dual-mode CMOS 2.4GHz transceiver consumes 65mA in RX and 78mA TX from a 3V supply. The receiver achieves typical sensitivity of -88dBm at 11Mb/s for 802.11b, -83dBm Bluetooth mode. minimum IIP3 is -8dBm, the transmitter delivers nominal output power 0dBm, with control range 20dB 2dB steps.
IRF2BPL mutation has been associated with a rare neurodevelopmental disorder abnormal movements, including dystonia. However, the role of in dystonia remains elusive. We aimed to investigate mutations Taiwanese cohort.
A quad-band 2.5G SoC integrates all the RF, DSP, ARM, audio and other baseband processing functions into a single 65nm CMOS die. The radio draws battery current of 49mA in RX-mode, 86mA GMSK TX-mode. low-IF receiver achieves sensitivity -110dBm at antenna, corresponding to noise figure 2.4dB device input. 8PSK ±400kHz modulation mask is -64.1/62.7dBc for high/low bands, with an RMS EVM 2.45/1.95%.
Based on the physical understanding of noise mechanisms in active mixers, a cancellation technique to reduce flicker-noise contribution switches Gilbert-type mixer is presented. A prototype double-balanced 0.13 /spl mu/m CMOS fabricated as proof concept. The circuit achieves corner almost an order-of-magnitude lower than that standard implementation without compromising linearity, gain, or power consumption.
This work presents a cellular transceiver capable of transmitting two simultaneous channels with an aggregate bandwidth up to 40 MHz, supporting 100 Mbps uplink rate. The transmitter has 8 RF output ports covering the transmit bands within 572-2100 MHz frequency range. It can support TX LTE-advanced Rel-12 Cat7, HSPA+ Rel-11, TDSCDMA Rel-9, and GSM/EDGE Rel-9. nm CMOS consumes 22 mA 27 in 3G LTE modes (at 0 dBm antenna power), respectively, including PLL, DCXO biasing for single channel.
A 0.18 /spl mu/m CMOS IEEE 802.11b SoC integrated all the radio building blocks including PA, PLL loop filter, and antenna switch, as well complete physical layer MAC sections. At 2.4 GHz, it dissipates 165 mW in receive-mode 360 transmit-mode from a 1.8 V supply. The receiver achieves typical NF of 6 dB, -88 dBm sensitivity at 11 Mbit/s rate. transmitter delivers nominal output power 13 dBm.
This work presents a cellular receiver capable of receiving three simultaneous channels with an aggregate bandwidth 60 MHz, enabling 300 Mbps downlink rate. The has 16 RF LNA ports covering the bands within 572-2700 MHz frequency range. It supports LTE-advanced Rel-12 Cat6, HSPA+ Rel-11, TD-SCDMA Rel-9, and GSM/EDGE Rel-9. 40 nm CMOS consumes 13.7 mA 17.6 battery current in 3G LTE modes, respectively, including PLL, DCXO, bia sing for single channel.
This article reviews transmitter topologies for radio transceivers with emphasis on cellular applications. In the first section it discusses different architectures and challenges in practical implementations. Then presents a as part of fully integrated transceiver GSM/GPRS/EDGE.
A fully integrated system-on-a-chip intended for use in IEEE 802.11b applications is built 0.18 /spl mu/m CMOS. All the radio building blocks, including PA, PLL loop filter, and T/R switch, as well complete physical layer MAC sections, have been into a single chip. The tuned to 2.4 GHz dissipates 165 mW receive-mode 360 transmit-mode. receiver achieves sensitivity of -88 dBm at 11 Mbps rate, transmitter delivers nominal output power 13 dBm.
This paper describes the design of a transmit PLL circuit at 24GHz in 0.13μm CMOS technology. is made with fully differential circuits to reject common mode noise. The VCO output frequency and IF 400 MHz. In order take advantage VCO, charge pump loop filter are developed. draws no DC current when lock. supply voltage for this 1.5V. bandwidth 500 KHz band phase noise 100 offset -112dBc. settling time 220 ns.