A5054250441- Radio Frequency Integrated Circuit Design
- Advanced Power Amplifier Design
- Microwave Engineering and Waveguides
- GaN-based semiconductor devices and materials
- Analog and Mixed-Signal Circuit Design
- Advancements in PLL and VCO Technologies
- Wireless Power Transfer Systems
- Electromagnetic Compatibility and Noise Suppression
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor Quantum Structures and Devices
- Advanced DC-DC Converters
- Ultra-Wideband Communications Technology
- Sensor Technology and Measurement Systems
- Full-Duplex Wireless Communications
- Photonic and Optical Devices
- Antenna Design and Analysis
- Wireless Communication Networks Research
- Pulsed Power Technology Applications
- Electrostatic Discharge in Electronics
- Superconducting and THz Device Technology
- Microwave Imaging and Scattering Analysis
- Metallurgy and Material Forming
- Semiconductor materials and devices
- Acoustic Wave Resonator Technologies
- Low-power high-performance VLSI design
Sharif University of Technology
2015-2024
Politeknik Negeri Sriwijaya
2021
Sriwijaya University
2020-2021
Universidad Michoacana de San Nicolás de Hidalgo
2012
Broadcom (Israel)
2008
Broadcom (United States)
2008
University of Southern California
2004-2007
Southern California University for Professional Studies
2006
In this brief, a design technique for tapered distributed low-noise amplifiers (LNAs) is presented. A circuit model developed gain and noise analysis of nonuniform amplifier (DA). It shown that by optimal tapering gate drain transmission lines transistors, the LNA can provide lower broadband average figure (NF) compared to uniform DA. proof-of-concept integrated implemented using 0.1-μm GaAs pHEMT process. The provides 15.2 dB 3-dB bandwidth 43.3 GHz. NF 2.3 minimum 2.0 are achieved over...
A 6-bit passive phase shifter for 2.5- to 3.2-GHz frequency band has been designed and implemented in a standard 0.18- μm CMOS technology. new switched-network topology proposed implementing the 5.625 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> shift step. The insertion loss of circuit is compensated with an on-chip bidirectional amplifier. measured return losses are better than 8 dB output 1-dB compression point +9.5 dBm transmit...
An X-band core chip is designed and fabricated in 0.18- CMOS technology, which can significantly reduce the monolithic microwave integrated circuit count required for realizing an active beam-former T/R module. The consists of two RX/TX paths, each includes a 6-b phase shifter, attenuator, along with input output amplifiers. A new architecture such system low loss 5.625° shift block are proposed. overall rms gain errors better than 2° 0.25 dB, respectively, both paths. path around 12 while...
The transformer-feedback (TRFB) interstage bandwidth enhancement technique for broadband multistage amplifiers is presented. Theory of the TRFB and design conditions maximum bandwidth, maximally flat gain, group delay are provided. It shown that can provide higher compared to conventional techniques based on reactive impedance matching networks. A three-stage low-noise amplifier (LNA) monolithic microwave integrated circuit with between its consecutive stages designed implemented in a 0.1-...
A pulse-based ultra-wideband transceiver (UWB-IR) operating in the 3.25-4.75 GHz band designed for low power and high data rate communication is implemented 0.18 mum CMOS technology. When at 1 Gbps rate, it dissipates 98 mW (98 pJ/b) receive-mode 108 (108 transmit-mode from a 1.8 V supply [1]. Compared to UWB transceivers reported literature, this chip lowest energy per bit. In addition, combination of frequency channelized architecture, high-linearity RF circuits, aggressive baseband...
This paper presents a harmonic termination technique for single- and multi-band high-efficiency class-F monolithic microwave integrated circuit (MMIC) power amplifiers (PAs). The network (HTN), realized with the minimum possible number of elements, can be used to terminate an arbitrary harmonics in single-band PA or multiple frequencies concurrent PA. drain gate bias lines are embedded HTNs obviate need RF chokes reduce chip area. A dual-band MMIC designed using proposed implemented 0.25- μm...
This paper presents an unilateralization technique for distributed amplifiers (DAs) based on the transformer coupling between gate and drain lines. Theoretical analysis of DA indicates that voltage waves in lines can be described by a system linear partial differential equations. The allows cancellation reverse transmission coefficient system. There is optimal value unilateralizes DA. derived terms gate-drain capacitance capacitances Using proposed technique, two monolithic microwave...
This paper presents a design methodology for class-J monolithic microwave integrated circuit (MMIC) power amplifiers (PAs). Theoretical derivations of optimum load impedances, output power, efficiency, and maximum bandwidth are described in presence nonlinear drain-source resistance transistors (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> ) . A procedure is developed ideal transistor sizing where concurrently stabilized sized to...
This paper presents the design procedure of monolithic microwave integrated circuit (MMIC) high-power amplifiers (HPAs) as well implementation high-efficiency and compact-size HPAs in a 0.25- μm AlGaAs-InGaAs pHEMT technology. Presented techniques used to extend bandwidth, improve efficiency, reduce chip area are described detail. The first HPA delivers 5 W output power with 40% power-added efficiency (PAE) frequency band 8.5-12.5 GHz, while providing 20 dB small-signal gain. second 8 35%...
In this paper, performance of class-J mode power amplifiers (PAs) is studied when a second-harmonic voltage component added to the input node device. Theoretical formulations for optimum load impedances, output power, and drain efficiency are developed case, it shown that inclusion proper at gate transistor improves power. To check accuracy theoretical analyses simulation results, proof-of-concept 1-GHz 0.65-W PA fabricated in 0.25-μm AlGaAs-InGaAs pHEMT technology. The nonlinear gate-source...
This paper presents the design and implementation of a distributed class-J power amplifier (DJPA) in 0.25-μm AlGaAs-InGaAs pHEMT technology. Class-J mode operation is introduced amplifiers (DPAs) to achieve high added efficiencies (PAEs) over wide frequency ranges. Extensive load-pull (LP) source-pull (SP) simulations are performed show that PAs less sensitive proper termination higher order harmonics, PAE output can be obtained even if second, third, fourth, fifth harmonics comprise real...
This paper presents a design procedure for wideband 6-18-GHz monolithic microwave integrated circuit highpower amplifier (HPA) in 0.25-μm AlGaAs-InGaAs pHEMT technology. The is mainly focused on the realization of passive circuits to provide required low-loss and impedance transformation networks. two-stage GaAs HPA achieves an average output power 39.6 dBm peak 40.5 at 11 GHz, pulsed mode operation, with small-signal gain S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This paper presents a methodology for the design of Ka/Q-band monolithic microwave integrated circuit (MMIC) high-power amplifiers (HPAs). Design techniques are introduced to reduce chip area and improve bandwidth (BW). These applied 31-39-GHz 5-W HPA implemented on 0.1-μm AlGaAs-InGaAs pseudomorphic HEMT (pHEMT) technology. With dimensions 3.35 × 3.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , achieves 24% average power-added...
In this paper, a thorough design procedure for concurrent of integrated antiparallel Schottky-diode-based limiter and low noise amplifier (LNA) is presented. The optimum number branches, the size diodes in each branch, width transmission line loaded by diode considerations input transistor LNA are discussed detail. To improve power handling with minimum impact on overall figure (NF), novel structure proposed where transistors utilized topology. A also introduced transistor-based limiter-LNA....
This paper presents a bandwidth enhancement technique for broadband Darlington amplifiers. A detailed analysis of the high-frequency performance amplifier and effect is provided. design procedure also given feedback amplifiers with gain flattening. single- three-stage proposed improvements are designed implemented in 0.25- μm AlGaAs-InGaAs pHEMT technology. The single-stage provides 6±0.4 dB small-signal frequency band 1-30 GHz. features 17.8±0.8 2-29 It gain-bandwidth product 217 GHz, which...
This paper presents two integrated concurrent dual-band class-J power amplifiers (PAs) in AlGaAs-InGaAs pHEMT technology. Design flexibility of space is employed to explore the availability a PA where center frequency second band twice first (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> = 2f xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ). The theoretical formulations are developed for f case, which it not feasible obtain high...
This paper presents a new method to enhance the efficiency of symmetrical doherty power amplifier (DPA) by fully utilizing current driving capability class-C biased peaking amplifier. In this method, with utilization passive voltage gain concept, input matching networks are designed in way that path experiences higher than carrier path, at high powers. As result, drive compensates for its lower gate bias and identical peak output currents both amplifiers can be achieved. For demonstration...
In this paper, the class-J mode of operation is investigated when sinusoidal, half-sinusoidal (HS), triangle, pulse, and reduced conduction angle voltage waveforms are shaped at gate node transistor. Output power, maximum power-added efficiency (PAE), large signal gain (LSG), load-pull contours presented compared for each input signal. It shown that PAE a power amplifier (PA) improved an HS realized This enhancement can also be observed pulse with 20% duty cycle, however, expense output LSG....
A wideband integrated delay chain chip with 5-bit main control, two error correction bits, maximum of 125- and 3.9-ps resolution, designed fabricated in a 0.18-μm CMOS technology is presented. This cascade seven passive internal-switched blocks which the five bits are based on novel structures. The proposed structures similar to second-, fourth-, sixth-order all-pass networks robust mismatch effects resistive parasitics transistor switches. Measurement results show 15.2-23.3-dB insertion...
An analytical approach for design optimization of multi-stage LNAs with common source topology is developed. This paper reviews and analyses simultaneous noise input impedance matching in three different topologies including amplifier inductive degeneration, resistive feedback dual order to achieve maximum available gain minimum possible figure (NF). A study on performed calculate optimum each stage overall NF while considering the that addition effect following stages. MATLAB was used...
In this paper, two output matching networks (OMNs) are proposed for integrated class-J and <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> mode power amplifiers (PAs). The first MN provides the required load impedances of (i.e., Z(f <sub xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> )=R xmlns:xlink="http://www.w3.org/1999/xlink">opt</sub> +jR Z(2f )=-j(3π/8)R ), whereas second realizes optimal PAs -jR )=j(3π/8)R ). Detailed...
This article proposes the theory and implementation of an even-harmonic class- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E$ </tex-math></inline-formula> CMOS oscillator that displays excellent phase noise performance. Starting from zero voltage switching (ZVS) derivative (ZDS) conditions, expressions for drain current waveforms are derived. Based on a 1:1 transformer, custom-designed tank is...
This radio integrates all the receive and transmit functions required to support a quad-band GSM/GPRS/EDGE application into single CMOS chip. Compared published work, this transceiver is implemented in low-cost digital 0.13 mum CMOS, achieves superior performance, yet has up 2x lower power consumption, key requirement cellular applications.
This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in 0.18-μm CMOS process. The performance BDDA is theoretically analyzed, optimum number gain stages (nopt), maximum achievable power (GP), circuit bandwidth are formulated. In addition, new formula for proper choice DA (i.e., n) offered where dc-power consumption (Pdc) also considered. optimizes GP/Pdc, it preferred over conventional nopt formula. To validate theoretical analyses, 2-12-GHz with...