A 6-bit passive phase shifter for 2.5- to 3.2-GHz frequency band has been designed and implemented in a standard 0.18- μm CMOS technology. new switched-network topology proposed implementing the 5.625 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> shift step. The insertion loss of circuit is compensated with an on-chip bidirectional amplifier. measured return losses are better than 8 dB output 1-dB compression point +9.5 dBm transmit...

This paper presents a design procedure for wideband 6-18-GHz monolithic microwave integrated circuit highpower amplifier (HPA) in 0.25-μm AlGaAs-InGaAs pHEMT technology. The is mainly focused on the realization of passive circuits to provide required low-loss and impedance transformation networks. two-stage GaAs HPA achieves an average output power 39.6 dBm peak 40.5 at 11 GHz, pulsed mode operation, with small-signal gain S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...

This paper presents a new method to enhance the efficiency of symmetrical doherty power amplifier (DPA) by fully utilizing current driving capability class-C biased peaking amplifier. In this method, with utilization passive voltage gain concept, input matching networks are designed in way that path experiences higher than carrier path, at high powers. As result, drive compensates for its lower gate bias and identical peak output currents both amplifiers can be achieved. For demonstration...

The hardware implementation of neural network has always been interest to the researchers as it can significantly increase efficiency and application networks due distributed nature Artificial Neural Networks (ANNs) in both memory computation. Direct ANNs also offer large gains when scaling sizes. Stochastic neurons are among most significant aspects machine learning algorithms very important different networks. In this paper, a model for stochastic neuron based on magnetic tunnel junction...

This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in 0.18-μm CMOS process. The performance BDDA is theoretically analyzed, optimum number gain stages (nopt), maximum achievable power (GP), circuit bandwidth are formulated. In addition, new formula for proper choice DA (i.e., n) offered where dc-power consumption (Pdc) also considered. optimizes GP/Pdc, it preferred over conventional nopt formula. To validate theoretical analyses, 2-12-GHz with...

This article presents the theory and implementation of a quadrature differential RF front-end receiver. Combining balun, low-noise amplifier (LNA), mixer, oscillator in single stage, proposed circuit, named Blixator, is well suited for low-power applications. The baseband's transimpedance (TIA) also shares part its dc current with Blixator cell, resulting sub-milliwatt power consumption. To avoid additional area by LO generation, I/Q signals are generated at RF, employing inductors already...

A wide input/output voltage range buck converter with adaptive light load efficiency improvement and seamless mode transition for high applications is presented. The proposed design uses a prediction structure to eliminate DC current sensor ensure in the 0.02 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 2 range. pulse width modulation (PWM) has been used near-full load....

This paper presents a general method for real-time adaptation of wireless receivers according to the prevailing reception conditions. In order maintain desired signal quality at minimum possible power dissipation, performs an optimal trade-off between noise, linearity, and consumption in building blocks receiver. is achieved by continuously monitoring signal-to-noise plus interference ratio (SNIR) accordingly tuning parameters embedded receiver design. A prototype DVB-H chip, implemented...

In this article, a design methodology is presented to realize integrated class-F high-power amplifiers (HPAs). A harmonic-control network (HCN) proposed present short- and open-circuit impedances each transistor employed in the output stage of HPA at 2f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> 3f frequencies. The HCN absorbs parasitic capacitance lends itself be absorbed matching power combiner networks, reducing die area HPA....

This study presents the analysis and reduction of vertical crosstalk in mixed-signal 3-D integrated circuits (3-D ICs) with multilayer graphene nanoribbon (MLGNR) multiwall carbon nanotube (MWCNT) interconnects. The 14-nm technology node is considered for both digital analog tiers. assessments are conducted regarding scattering parameters (S-parameters) equivalent circuit model transmission lines using Advanced Design System (ADS) tool. Our studies demonstrate that MLGNR lead to lower...

In this paper, two low-power inductorless low-noise amplifiers (LNAs) for multi-standard wireless applications are presented. the first proposed design, outputs of complementary NMOS and PMOS common-gate stages combined to reduce power consumption facilitate dc biasing. Also, passive Gm-boosting is applied core transistors improve noise performance. As a result these techniques, minimum NF 2.6 dB achieved, while consuming only 1 mA from 1.8 V supply. second both active techniques input CG...

A highly linear X-band low-noise amplifier (LNA) is proposed and implemented in a standard 0.18-μm CMOS technology. The LNA features both high- low-gain operation modes. In its normal high-gain mode, the shows small-signal gain of 13.6 dB with an IIP3 +9.5 dBm noise figure 4.7 dB. two-stage draws 90 mA from 3.3-V power supply to achieve +14.8 output P1dB (+2.2 input P1dB). reduced by about 10 further enhance linearity accommodate very large blockers. Accordingly, enhanced +13.7 while...

A CMOS fully differential UHF variable gain amplifier for use in a direct-conversion DVB-H receiver is presented employing input devices with aspect ratios. High linearity achieved by reducing the transconductance of transistors lower settings. It shown that this technique has better and noise performance compared to conventional methods which reduction performed at preceding stages. Implemented TSMC 0.18-mum process, inductorless RF VGA covers voltage ranging from 15.5 dB -6.5 maximum IIP3...

This paper presents a method for optimizing SFDR in differential active-RC filters. Simple analytical expressions noise and third-order intermodulation (IM3) distortion filters are derived. The nonlinear behavior of two-stage Miller-compensated op amps, which extensively used implementations, is also modeled. These models to maximize by means proper admittance scaling the share each amp total power consumption. It shown that both consumption filter its area can be significantly reduced,...

This paper presents a new fully-integrated CMOS single-to-differential low-noise amplifier (LNA) topology for cognitive radios. Operating from 50 MHz to 5 GHz, the proposed wideband LNA uses two current-reuse shunt-feedback (SFB) amplifiers as core circuit and an inverter active balun. The transconductance of is boosted by utilizing both nMOS pMOS transistors in complementary structures. Designed TSMC 0.18 μm technology, achieves voltage gain 25.3 dB noise figure 3.6 5.0 dB, with power...

Summary In this paper, a method for 3 ‐th ( ) harmonics rejection in 6 ‐path filters is proposed, and the related analysis provided. Using single‐ended‐input to differential‐output structure, filter selectivity around even are also suppressed. Accordingly, proof‐of‐concept band‐pass designed, postlayout simulations 90‐nm CMOS technology carried out, which covers an input frequency range from 200 MHz 1.2 GHz with channel bandwidth of 10 15.5 MHz. The achieved third harmonic at 1‐GHz local...

This article presents analyses of the Integrated buck-zeta converter at continuous conduction mode (CCM). is implemented by adopting a buck to conventional zeta converter. In other words, this circuit designed eliminating an H-bridge cell transistor and diode from DISO topology. Reducing number components increases efficiency. The output voltage polarity both stages are positive, unlike any multi-port buck-boost Cuk topologies. Compared boost SEPIC converters, serializing input sources...

In this paper, a detailed analysis is presented for the continuous conduction mode (CCM) operation of double-input/double-output DC/DC converter (DIDOC), which consists two H-bridge cells, buck converter, and zeta converter. The utilized by applying non-interleaved switching pattern on transistors circuit. Hence, can be implemented adopting low-pass filter to other cell. whole operated either in step-up or step-down conditions. proposed created based DISO buck-boost topologies. Compared...

An ultra-low-noise buck converter for noise-sensitive applications is presented, which utilizes a novel pseudo average current-mode control (ACMC) with an adaptive ramp generator to decrease the baseband noise. Also, in order suppress electromagnetic interference (EMI) and high-frequency spurs, spread spectrum secondary filter are used, respectively. The proposed ACMC suppresses switching frequency perturbation effect on output voltage, as result condition, only small amount of noise added...

This paper presents a double-input/single-output DC/DC Converter (DISOC) in continuous conduction mode (CCM) by applying non-interleaved switching pattern on the transistors of circuit. The converter can be utilized either step-up or step-down conditions. proposed is created combining H-bridge cells and zeta converter, based DISO buck-boost topologies. In comparison to converters, has positive output voltage, which required many applications. addition, connecting input voltage sources series...

Summary In this paper, a band‐pass filter with tunable bandwidth and the center frequency is introduced, which employs N‐path N × M‐path passive mixer structures, for multiband multistandard wireless receivers. The of proposed from 0.1 to 1 GHz, while its also adjustable 6% 34% at 100 MHz. passband ripple reduced by applying Miller compensation technique, resulting in worst‐case only 1.6 dB over entire tuning range. An additional eight‐path utilized input circuit, highly improves out‐of‐band...