The parameter extraction of device models is critically important for circuit simulation. in the existing software are physics-based analytical models, or embedded Simulation program with integrated emphasis (SPICE) functions. programming implementation tedious and error prone, while it time consuming to run model evaluation by calling SPICE. We propose a novel modeling technique based on neural network (NN) optimal parameters this paper, further integrate NN into software. does not require...

Abstract Three new chiral stationary phases ( CSPs ) for high‐performance liquid chromatography were prepared from R ‐(3,3'‐halogen substituted‐1,1'‐binaphthyl)‐20‐crown‐6 (halogen = Cl, Br and I). The experimental results showed that ‐(3,3'‐dibromo‐1,1'‐binaphthyl)‐20‐crown‐6 CSP ‐1 possesses more prominent enantioselectivity than the two other halogen‐substituted crown ether derivatives. All twenty‐one α ‐amino acids have different degrees of separation on...

Multivariate calibration models are constructed through the use of Gaussian basis functions to extract relevant information from single-beam spectral data. These related by analogy optical filters and offer a pathway direct implementation model in spectrometer hardware. The determined numerical optimization procedure employing genetic algorithms. This methodology is demonstrated development quantitative near-infrared spectroscopy. Calibrations developed for determination physiological levels...

SPICE model is one of the key technical connections between integrated-circuit technology community and design community. Design requires accurate parameters so as to make difference spec practical minimized possible. To get parameters, optimization algorithms are used for parameter extraction. A parallel hybrid evolutionary algorithm based chaos-GA-PSO presented extraction, which gets leverage advantages from chaos algorithm, genetic particle swarm optimization, overcomes their respective...

Considering that power consumption (PC) is an extremely important indicator in digital circuit design, lower PC has always been our pursuit. and supply voltage are positively correlated, this case, we must reduce the operating of circuit. However, as continues to decrease, various secondary effects process variations become increasingly influential, making delay distribution its statistical characteristics more difficult predict. In paper, inverse Gaussian used model propagation delay....

This paper proposes a compact, physics-based current model for fully depleted silicon-on-insulator (FDSOI) MOSFETs and applies it to delay variability analysis. An analytical method is applied avoid the numerical iterations required in evaluation of surface potential, which directly improves computational efficiency. The accuracy explicit potential approximation 190.3 nV, allows fast convergence. Surface calculations achieve 1.8× 1.4× acceleration compared with BSIM-IMG, respectively. To...

Process variation results in up to an order of magnitude Ion/Ioff ratios, which significantly depresses the yield sub-threshold circuits. This paper presents low power adders using sense amplifier-based pass transistor logic (SAPTL). Based on simulations 130nm CMOS process, proposed two-phase synchronous SAPTL adder exhibits stronger robustness process variations when compared ripple carry standard cell And based ADSA-SAPTL features much less consumption than adder.

It is time-consuming to obtain the matched devices by manual analysis and place them in hand for analog circuits of mixed signal system. To achieve high performance, placement a key point layout design circuits. In order simplify design, it necessary realize procedure automatically. this paper, method automatic circuit provided, as well an efficient algorithm device groups. The experimental results verify

The memory wall bottleneck has caused a large portion of the energy to be consumed by data transfer between processors and memories when dealing with data-intensive workloads. By giving some processing abilities memories, processing-in-memory (PIM) is promising technique alleviate bottleneck. In this work, we proposed novel PIM architecture employing ferroelectric field-effect transistors (FeFETs). design, named FePIM, able perform in-memory bitwise logic add operations two selected rows or...

In this paper, we present a novel method of analog circuit schematic synthesis, which bridges topology synthesis and sizing & layout in flow. Compared with traditional it brings templates-in, functionality analysis partitioning for new hierarchy, constraint generation, port analysis, analog-aware identification into the enable symbol generation cells, placement, wire routing based on functionality, types, other constraints, also constraints sizing, floor-planning, optimization are identified...

This paper presents a method of tuning the gate length and width in standard cell for reuse, which includes algorithm auto-identification, obtaining information locations and/or sizes related layout patterns. Existing layouts cells are reused to design new cells. Experimental results show that this can improve efficiency designs facilitate generation satisfying requirements physical optimization.

Analog circuit synthesis is a very important step of analog design automation flow. Due to the great effects on performance degradation from parasitic, it time-consuming task, especially when feature size becoming smaller and smaller, operation frequency higher higher, scale larger larger. In this paper, we present parallel flow with combination functionality analysis based partitioning, spec decomposition, test bench generation, evaluation equation generation; makes high complex large...

This paper proposes a 16 bit subthreshold adder design using bootstrapped sense amplifier-based pass transistor logic (bootstrapped SAPTL) to overcome serious performance degradation and enhance the immunity process variations in region. Through employing amplifier including voltage boosting part adopting an architecture based on SAPTL, significant improvements energy efficiency can be achieved. A case study of adders SMIC 130 nm technology demonstrated that proposed outperformed other works...