Jun Tao

ORCID: 0000-0001-8742-687X
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About
Contact & Profiles
Research Areas
  • Low-power high-performance VLSI design
  • VLSI and FPGA Design Techniques
  • VLSI and Analog Circuit Testing
  • Probabilistic and Robust Engineering Design
  • Advancements in Photolithography Techniques
  • Advancements in Semiconductor Devices and Circuit Design
  • Analog and Mixed-Signal Circuit Design
  • Integrated Circuits and Semiconductor Failure Analysis
  • Radio Frequency Integrated Circuit Design
  • Radiation Effects in Electronics
  • Optimal Experimental Design Methods
  • Advanced Multi-Objective Optimization Algorithms
  • Advanced Surface Polishing Techniques
  • Model Reduction and Neural Networks
  • Control Systems and Identification
  • 3D IC and TSV technologies
  • Innovation and Knowledge Management
  • Network Security and Intrusion Detection
  • Advanced Numerical Analysis Techniques
  • Analytical Chemistry and Sensors
  • Manufacturing Process and Optimization
  • Microwave Engineering and Waveguides
  • Semiconductor Lasers and Optical Devices
  • Advanced Wireless Communication Techniques
  • Numerical Methods and Algorithms

Fudan University
2016-2025

Shanghai Fudan Microelectronics (China)
2015-2024

Huawei Technologies (China)
2023-2024

State Key Laboratory of ASIC and System
2009-2023

Zhejiang University
2023

Guilin University of Technology
2020-2023

Institute of Microelectronics
2023

Anhui Institute of Information Technology
2023

Nanjing University of Aeronautics and Astronautics
2023

Southern California University for Professional Studies
2023

Due to the movement expressiveness and privacy assurance of human skeleton data, 3D skeleton-based action inference is becoming popular in healthcare applications. These scenarios call for more advanced performance application-specific algorithms efficient hardware support. Warnings on health emergencies sensitive response speed require low latency output early detection capabilities. Medical monitoring that works an always-on edge platform needs system processor have extreme energy...

10.1109/tbcas.2021.3064841 article EN IEEE Transactions on Biomedical Circuits and Systems 2021-03-09

The paper introduces the conception, origin, development and current situation of functionally gradient materials (FGM). characteristics advantages FGM are shown completely by comparing it with other materials. main research field is expatiated from three aspects design, preparation evaluation. application trend prospected finally in paper.

10.1109/icicee.2012.271 article EN International Conference on Industrial Control and Electronics Engineering 2012-08-01

This article presents a wideband, low-jitter frequency synthesizer utilizing dual-mode voltage-controlled oscillator (VCO). Mode imbalance in the VCO is analyzed theoretically and compensated through proposed symmetric figure-8 transformer capacitor arrays. The compact mode-switching circuitry fundamentally eliminates mode ambiguity multi-mode autonomous circuits. A computer-aided algorithm based on sequential least-squares programming (SLSQP) hierarchical optimization method developed to...

10.1109/jssc.2023.3242617 article EN IEEE Journal of Solid-State Circuits 2023-02-16

In this paper, we propose an efficient performance trade-off modeling method for analog circuit based on Bayesian Neural Network (BNN). First, use a single BNN to simultaneously model multiple performances of interest (PoIs) circuit. This can be trained by using novel automatic differential variational inference (ADVI) with affordable computational cost. Next, the extracted embedding into optimization framework combined modified multi-objective evolutionary method. Since correlations among...

10.1109/iccad45719.2019.8942174 article EN 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2019-11-01

Recently model order reduction techniques for second-order systems have obtained many research interests the simulation of RCS interconnect circuits employing susceptance elements. In this paper, we propose a Block SAPOR (Block Second-order Arnoldi method Passive Order Reduction) Multi-Input Multi-Output Circuits. The proposed algorithm can simultaneously guarantee passivity and achieve higher accuracy than first technique PRIMA. Most importantly, reduced system matrices by preserve...

10.1145/1120725.1120815 article EN 2005-01-01

To reduce chip-scale topography variation in chemical mechanical polishing process, dummy fill is widely used to improve the layout density uniformity. Previous researches formulated density-driven problem as a standard linear program (LP). However, solving huge formed by real-life designs very expensive and has become hurdle deploying technology. Even though there exist efficient heuristics, their performance cannot be guaranteed. Furthermore, can also change interconnect coupling...

10.1109/tcad.2010.2088030 article EN IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2011-02-18

In this paper, a graph-constrained sparse performance modeling method is proposed for analog circuit optimization. It builds polynomial models constrained by an acyclic graph. These can be used to solve optimization problems within local design spaces using convex semidefinite programming relaxation both efficiently and robustly. Our numerical examples demonstrate that the quickly accurately converge superior solution circuits while conventional fails work.

10.1109/tcad.2018.2848590 article EN publisher-specific-oa IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2018-06-18

Reconfigurable radio frequency (RF) system is an emerging component to mitigate the growing engineering cost for wireless chip design. In this paper, we propose a new methodology efficient programming of reconfigurable RF receiver. The proposed method facilitated by two novel techniques: two-phase relaxation search and Pareto-based space reduction. Our numerical experiments demonstrate that more robust (i.e., close global optimum) and/or with low computational cost) than other traditional...

10.1109/aspdac.2014.6742899 article EN 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) 2014-01-01

Approximate computing is an efficient approach to reduce the design complexity for error-resilient applications. Multipliers are key arithmetic units in many applications, such as deep neural networks (DNNs) and digital signal processing (DSP) systems. In this article, open-source adaptable approximate multiplier driven by input distribution polarity proposed generate optimized multipliers trade off between application-level performance hardware cost. The method minimizes average square of...

10.1109/tvlsi.2022.3197229 article EN IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2022-08-25

In this paper, a novel Asymptotic Probability Approximation (APA) method is proposed to estimate the overall rare probability of correlated failure events for complex circuits containing large number replicated cells (e.g., SRAM bit-cells). The key idea APA approximate circuit rate based on set carefully defined events. An efficient Hierarchal Subset Simulation (H-SUS) developed calculate aforementioned and statistical methodology further confidence interval APA. Our numerical experiments...

10.1145/2966986.2967029 article EN 2016-10-18

In nanometer technologies, process variations possess growing nonlinear impacts on circuit performance, which causes critical path delays of combinatorial circuits variate randomly with non-Gaussian distribution. this paper, we propose a novel clock skew scheduling methodology that optimizes timing yield by handling distributions delays. Firstly general formulation the optimization problem is proposed, covers most previous formulations and indicates their limitations statistical...

10.1145/1391469.1391525 article EN 2008-06-08

In this paper, an iterative method is proposed for the optimization of wideband voltage-controlled oscillators (VCOs). The attempts to improve two significant performance metrics VCOs, i.e., nonuniform band distribution and nonconstant tuning gain KVCO. To address these nonideality issues, we introduce deviation as a prior knowledge calibration in each iteration step. optimal capacitor array weighting plan can be asymptotically approached through multiple iterations. demonstrate efficacy...

10.1109/tcad.2018.2878161 article EN IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2018-11-08

Through-silicon via (TSV) with flip-chip packaging is a technology that enables vertical integration of silicon dies, forming single 3-D IC stack. A practical model for preplaced TSV assignment nets proposed this technology. We prove the general problem more than two dies NP-complete. An integrated algorithm combines shortest path search, bipartite matching, min-cost max-flow calculation, and postprocessing developed. Experimental results using actual testing data demonstrate our flow...

10.1109/tvlsi.2013.2246876 article EN IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2013-03-11

This poster presents a visualization tool SHAvisual for instructors to teach and students learn the SHA-512 algorithm visually with demo practice modes. will also discuss some findings of classroom use student reactions, which are very positive encouraging.

10.1145/2591708.2602663 article EN 2014-01-01

In this paper, a general rough-pad model is proposed for the chemical mechanical polishing (CMP) process. The has several advantages over existing models. First, height distribution functions and autocorrelation are used to describe pad surface, which easier obtain than asperity curvature distributions in Second, spectral representation technique nonlinear transformation method allow surfaces with surface functions. Thus, no assumption made on geometry statistics of pad. A conjugate-gradient...

10.1149/1.3133238 article EN Journal of The Electrochemical Society 2009-01-01

In this paper, a novel Asymptotic Probability Estimation (APE) method is proposed to estimate the probability of correlated rare failure events for complex integrated systems containing large number replicated cells. The key idea approximate rate entire system by solving set nonlinear equations derived from general analytical model. An error refinement based on Look-up Table (LUT) further developed improve numerical stability and, hence, reduce estimation error. Our experiments demonstrate...

10.1145/3061639.3062217 article EN 2017-06-13

Efficiently optimizing large-scale, complex analog systems requires to know the performance tradeoffs for various circuit blocks. In this paper, we propose a radically new approach tradeoff modeling. Our key idea is broadly search rich design knowledge from Internet, and then mathematically encode as high-dimensional curves that are referred Pareto fronts in literature. Toward goal, several novel numerical algorithms, such sparse regression semi-infinite programming, developed order...

10.1109/tcad.2015.2449240 article EN IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2015-06-23

In this paper, we propose a novel spatial variation modeling method based on hidden Markov tree (HMT) for nanoscale integrated circuits, which could efficiently improve the accuracy of full-wafer/chip variations recovery at extremely low measurement cost. Applying method, HMT is introduced to set up statistical model coefficients after exploring underlying correlated representation in frequency domain. Accordingly, two key inherent properties coefficients, i.e., correlations and sparse...

10.1109/tcad.2015.2481868 article EN IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2015-09-24

In this paper, we propose an adaptive stochastic collocation method for block-based statistical static timing analysis (SSTA). A novel is proposed to perform SSTA with delays of gates and interconnects modeled by quadratic polynomials based on homogeneous chaos expansion. order approximate the key atomic operator MAX in full random space during analysis, adaptively chooses optimal algorithm from a set methods considering different input conditions. Compared existing methods, including one...

10.1109/isqed.2008.4479699 article EN 2008-03-01
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